Patents Examined by Chae Ko
  • Patent number: 9405755
    Abstract: A method implemented by a computer includes receiving a log file with log file data characterizing the operation of a system. A normalized format for the log file data is proposed. User input on the normalized format is solicited. The normalized format is set. The log file data is converted to the normalized format. A visualization application operative with the normalized format is selected. The visualization application supplies visualizations of the log file data.
    Type: Grant
    Filed: July 24, 2014
    Date of Patent: August 2, 2016
    Assignee: Initial State Technologies, Inc.
    Inventors: James Ray Bailey, David Leo Sulpy, Adam Matthew Reeves
  • Patent number: 9405651
    Abstract: A computer implemented method includes receiving a log file with a textual description of the operation of a system. The textual description is converted to event waveforms, where each event waveform has a time axis and event indicia. A representation of the event waveforms is supplied.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: August 2, 2016
    Assignee: Initial State Technologies, Inc.
    Inventor: James Ray Bailey
  • Patent number: 9405610
    Abstract: A computer implemented method includes receiving a data stream from a client device. The data stream includes a textual description of the operation of a system. The textual description includes at least one textual instruction. The textual description is converted to event waveforms where each event waveform has a time axis and event indicia. The textual instruction is rendered as an ideogram associated with the event waveforms. A representation of the event waveforms and the ideogram is supplied.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: August 2, 2016
    Assignee: Initial State Technologies, Inc.
    Inventors: James Ray Bailey, Adam Matthew Reeves
  • Patent number: 9406337
    Abstract: The object of the present invention is to provide a disk array device, a failure path specifying method and a program thereof capable of specifying a physical interconnection path where failures occurred.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: August 2, 2016
    Assignee: NEC CORPORATION
    Inventor: Shoichi Nomura
  • Patent number: 9389977
    Abstract: Provided are fault injection testing apparatus and method which inject faults that may occur in a system or a source file that a user wants to examine and examine which processes are performed by the system or source file when the faults occur.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: July 12, 2016
    Assignee: Altibase Corp.
    Inventors: Shi Bok Jang, Jae Hyo Lee, Ying Zhe Ma
  • Patent number: 9389961
    Abstract: Various systems, methods and apparatuses for creating network isolation spanning physical and virtual hosts are presented. In one embodiment, network isolation may be created between a primary (e.g., production) site and a secondary (e.g., a disaster recovery or sandbox) site. The network isolation allows testing (or other uses) on the secondary site to be non-disruptive to the normal operations of the sites, including the ability to failover during testing. Such non-disruptive network isolation allows certain communications to continue, especially communications between ports having replicated data. The network isolation may be customized in various other ways to allow certain communications to continue while preventing other communications. This invention can be used to validate application readiness, as well as to validate data correctness of individual tiers, and may be used with systems that contain multiple tiers, and include physical hosts, virtual hosts, and/or combinations of both.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: July 12, 2016
    Assignee: Veritas Technologies LLC
    Inventors: Swapnil Patankar, Shrikant Ghare
  • Patent number: 9378102
    Abstract: A system on a chip (SoC) for providing safety hardware fault tolerance and/or safety software fault tolerance includes a first safety sub-system having a first safety channel; a second safety sub-system having a second safety channel; and a third sub-system. The first safety sub-system is independent of the second safety sub-system to allow the second safety sub-system to communicate through the second safety channel when the first safety sub-system or the third subsystem fails, and further to allow the first safety sub-system to communicate through the first safety channel when the second safety sub-system or the third subsystem fails.
    Type: Grant
    Filed: August 6, 2014
    Date of Patent: June 28, 2016
    Assignee: XILINX, INC.
    Inventors: Sagheer Ahmad, Bradley L. Taylor, Giulio Corradi
  • Patent number: 9366726
    Abstract: The disclosure describes a novel method and apparatus for improving the operation of a TAP architecture in a device through the use of Command signal inputs to the TAP architecture. In response to a Command signal input, the TAP architecture can perform streamlined and uninterrupted Update, Capture and Shift operation cycles to a target circuit in the device or streamlined and uninterrupted capture and shift operation cycles to a target circuit in the device. The Command signals can be input to the TAP architecture via the devices dedicated TMS or TDI inputs or via a separate CMD input to the device.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: June 14, 2016
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 9367410
    Abstract: The disclosure is directed to failover mechanisms in a distributed computing system. A region of data is managed by multiple region servers. One of the region servers is elected as a “leader” and the remaining are “followers.” The leader serves the read/write requests from a client. The leader writes the data received from the client into the in-memory store and a local write-ahead log (“WAL”), and synchronously replicates the WAL to the followers. A region server designated as an “active” region server synchronizes a distributed data store with the data from the WAL. Active witness followers apply the data from the WAL to their in-memory store while shadow witness followers do not. Different types of servers provide failover mechanisms with different characteristics. A leader is elected based on their associated ranks—higher the rank, higher the likelihood of electing itself as a leader.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: June 14, 2016
    Assignee: Facebook, Inc.
    Inventors: Liyin Tang, Rishit Manit Shroff, Amitanand S. Aiyer, Arjen Roodselaar
  • Patent number: 9361177
    Abstract: A system comprising a plurality of storage systems, which uses storage devices of multiple levels of reliability. The reliability as a whole system is increased by keeping the error code for the relatively low reliability storage disks in the relatively high reliability storage system. The error code is calculated using hash functions and the value is used to compare with the hash value of the data read from the relatively low reliability storage disks.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: June 7, 2016
    Assignee: Hitachi, Ltd.
    Inventors: Tomohiro Kawaguchi, Akira Yamamoto
  • Patent number: 9354981
    Abstract: A memory module stores working data that includes data units. A storage system stores recovery data that includes sets of one or more data units. Transferring data units between the memory module and the storage system includes: maintaining an order among the data units included in the working data, the order defining a first contiguous portion and a second contiguous portion; and, for each of multiple time intervals, identifying any data units accessed from the working data during the time interval, and adding to the recovery data a set of two or more data units including: one or more data units from the first contiguous portion including any accessed data units, and one or more data units from the second contiguous portion including at least one data unit that has been previously added to the recovery data.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: May 31, 2016
    Assignee: Ab Initio Technology LLC
    Inventor: Joseph Skeffington Wholey, III
  • Patent number: 9348714
    Abstract: One or more techniques and/or systems are provided for load balancing between storage controllers. For example, a first storage controller and a second storage controller may be configured at a first storage site according to a high availability configuration, and may be configured as disaster recovery partners for a third storage controller and a fourth storage controller at a second storage site. If the first storage controller fails, the second storage controller provides failover operation for a first storage device. If a disaster occurs at the second storage site, the second storage controller provides switchover operation for a third storage device and a fourth storage device. Responsive to the first storage controller being restored, the third storage device may be reassigned from the second storage controller to the first storage controller for load balancing at the first storage site during disaster recovery of the second storage site.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: May 24, 2016
    Assignee: NetApp Inc.
    Inventors: Abhishek Jain, Chaitanya Patel, Deepan Natesan Seeralan, Linda Ann Riedle
  • Patent number: 9336093
    Abstract: An information processing system includes a plurality of storage devices, a plurality of data access devices, and a first processor. The first processor selects, when a first data access device permitted to access data in a first storage device fails, a second data access device other than the first data access device. The first data access device is included in the plurality of data access devices. The first storage device is included in the plurality of storage devices. The second data access device is included in the plurality of data access devices. The first processor permits the second data access device to access data in the first storage device. The first processor updates correspondence information, which indicates the first data access device as a transfer destination of a request to access first data in the first storage device, to indicate the second data access device as the transfer destination.
    Type: Grant
    Filed: May 9, 2013
    Date of Patent: May 10, 2016
    Assignee: FUJITSU LIMITED
    Inventor: Yotaro Konishi
  • Patent number: 9336103
    Abstract: A DR site is maintained containing multiple VMs distributed across multiple hosts to which a multi-tiered application can be failed over from a production site. A network bubble is created in which the multi-tiered application can be fire drill tested without conflicting with the production instance. Each VM is cloned, and cloned VMs communicate using private IP addresses. A virtual switch is created on each host, and configured for cloned VM communication. On each host, a virtual router is configured with both a public virtual adapter and a private virtual adapter. The source VMs communicate using public IP addresses over the physical channel, via the external virtual switches on the hosts, and are available for failover from the production site. The cloned VMs communicate using private IP addresses via the virtual switches and private virtual adapters of the virtual routers, thereby forming the network bubble.
    Type: Grant
    Filed: April 2, 2014
    Date of Patent: May 10, 2016
    Assignee: Veritas US IP Holdings LLC
    Inventors: Sunil Hasbe, Hermesh Gupta, Mandar Kashelikar
  • Patent number: 9332450
    Abstract: Method and system for a test process. The method may include performing tests on one or more units under test (UUTs). At least one test on one or more UUTs may be performed. A signal may be acquired from the UUT. A reference signal may be retrieved. The reference signal may be derived from a transmitted signal characteristic of the UUT. The signal may be analyzed with respect to the reference signal. Results, useable to characterize the one or more UUTs, from performing the at least one test on the one or more UUTs may be stored. The reference signal may be derived from an initial test and may be stored for subsequent retrieval. A respective reference signal may be retrieved for all UUTs of the one or more UUTs for a respective test. The signal may be a radio frequency signal. The UUT may be a wireless mobile device.
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: May 3, 2016
    Assignee: National Instruments Corporation
    Inventors: Craig E. Rupp, Gerardo Orozco Valdes, I. Zakir Ahmed, Vijaya Yajnanarayana
  • Patent number: 9323597
    Abstract: Flow based fault testing is provided. A logical constraint model or a state model (LS model) can be generated based on logic/state characteristics of a system under test (SUT). The LS model can be generated from logical constraint grammar statements. The logical constraint grammar can be parsed as part of a pre-test analysis to seek faults related to the logic or states of the model. The inputs and outputs related to the SUT can be employed to determine faults, including post-test analysis for faults. The disclosed subject matter can capture in an automated or semi-automated manner faults that can be missed in more conventional fuzz testing. Further, flow based fault testing can be employed alone, along with, or in combination with conventional fuzz testing.
    Type: Grant
    Filed: May 9, 2013
    Date of Patent: April 26, 2016
    Assignee: PEACH FUZZER LLC
    Inventor: Michael Eddington
  • Patent number: 9326371
    Abstract: An information handling system includes a printed circuit board (PCB) including a signal path with a trace coupled to a source, another trace coupled to a load, a tuned stub, and a via connecting the traces and the tuned stub. A method includes providing a signal path on a PCB with a trace coupled to a source, a trace coupled to a load, a tuned stub, and a via connecting the traces and the tuned stub, driving a signal on the signal path, and adjusting the tuned stub length so that the signal is unchanged between the source and the load. A PCB includes a signal path between a source and a load with two traces and a via, and a tuned path between the source and the load with the two traces, another trace, and the via, the length of the tuned path being a half wavelength stub.
    Type: Grant
    Filed: September 10, 2008
    Date of Patent: April 26, 2016
    Assignee: DELL PRODUCTS, LP
    Inventors: Sandor T. Farkas, Girish K. Singh
  • Patent number: 9323630
    Abstract: Systems, methods, and firmware for recovery of data from storage devices are provided herein. In one example, a data storage device is provided. The data storage device includes a storage portion and a cache portion which caches data intended for storage in the storage portion. Responsive to a recovery read command identifying requested data, the data storage device retrieves stored data corresponding to the requested data from the storage portion without retrieving cached data corresponding to the requested data from the cache portion that supersedes at least a portion of the stored data. Responsive to a cache block list command, the data storage device transfers a list identifying one or more cached blocks of the cached data. Responsive to a read command that identifies at least one cached block, the data storage device retrieves the at least one cached block.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: April 26, 2016
    Assignee: HGST Netherlands B.V.
    Inventors: Cyril Guyot, Zvonimir Bandic
  • Patent number: 9317366
    Abstract: A buffer integrated circuit device. The device comprising an output driver formed on the substrate member, the output driver having at least a command bus and an address bus. The device has a protocol and parity checking block (“Block”). The device has a table configured in the block. The table is programmable with a plurality of timing parameters. The device has a memory state block coupled to the table and a command history table coupled to the table to process protocol information for all commands that pass through the Block. The buffer integrated circuit device utilizes the protocol checking functionality to prevent failure propagation and enables data protection even in the case of host memory controller failure or system-level failure of any signal or signals on the command, control and address bus from the host memory controller to the buffer integrated device.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: April 19, 2016
    Assignee: INPHI CORPORATION
    Inventor: David Wang
  • Patent number: 9319460
    Abstract: An information processing method includes executing a processing corresponding to a first request of a terminal apparatus using a first information processing apparatus, when a fault occurs in the first information processing apparatus, transmitting an apparatus information that identifies the first information processing apparatus from a second information processing apparatus to the terminal apparatus, after receiving the apparatus information by the terminal apparatus, discarding data transmitted from the first information processing apparatus to the terminal apparatus, transmitting, from the terminal apparatus to the second information processing apparatus, a response notification indicating that the apparatus information is received by the terminal apparatus, and after receiving the response notification by the second information processing apparatus, executing the processing corresponding to a second request of the terminal apparatus using the second information processing apparatus.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: April 19, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Shinji Yamabiraki, Takeshi Yamazaki, Tamaki Tanaka