Abstract: A method of validating functional testing of system circuitry on an integrated circuit chip, the system circuitry configured to perform a plurality of functions, the integrated circuit chip further comprising debugging circuitry under the control of a debug controller, the debugging circuitry comprising at least one debug unit. The method comprises: at the system circuitry, performing one of the plurality of functions; applying a debug configuration to the at least one debug unit; and at the at least one debug unit, monitoring for a characteristic in the system circuitry's performance of the one of the plurality of functions according to that debug configuration, and reporting to the debug controller.

Abstract: A storage device includes one or more storages and one or more control devices to control writing data to and reading data from one of the storages. Each of the control devices includes a memory, a memory controller, and a processor. The memory controller controls writing data to and reading data from the memory. The processor determines whether the memory and the memory controller have error correcting functions respectively. The processor determines, when at least one of the memory and the memory controller does not have an error correcting function, whether an error is detected in first data expanded in a first memory region of the memory. The first data includes an error detecting code. The processor saves, when no error in the first data has been detected, the first data into a second memory region of the memory. The second memory region is different from the first memory region.

Abstract: A system is provided for managing error reporting in a network. The system comprises a buffer for storing traps, a timer that measures a time period and a buffer manager that compares incoming traps to traps already stored in the buffer. An incoming trap is stored in the buffer if it is determined that the incoming trap is not similar to traps already stored in the buffer. The buffer is cleared after the time period measured by the timer has elapsed.

Abstract: A method begins by a processing module sending list digest requests to a set of dispersed storage (DS) units. The method continues with the processing module receiving list digest responses from at least some of the set of DS units and determining whether an inconsistency exists between first and second list digest responses of the list digest responses. The method continues with the processing module requesting at least a portion of each of the slice name information lists from first and second DS units of the set of DS units and identifying a slice name information error associated with the inconsistency based on the at least a portion of each of the slices name information lists of the first and second DS units when the inconsistency exists between first and second list digest responses of the list digest responses.

Abstract: The disclosure describes a novel method and apparatus for improving the operation of a TAP architecture in a device through the use of Command signal inputs to the TAP architecture. In response to a Command signal input, the TAP architecture can perform streamlined and uninterrupted Update, Capture and Shift operation cycles to a target circuit in the device or streamlined and uninterrupted capture and shift operation cycles to a target circuit in the device. The Command signals can be input to the TAP architecture via the devices dedicated TMS or TDI inputs or via a separate CMD input to the device.

Abstract: A method and apparatus for determining one or more compression parameters suitable to compress a class of signals, may include inputting a test data set, being representative of a data set to be compressed, characterizing the test data, selecting a compression algorithm, calculating a distortion level to be used in determining the compression ratio (or a compression ratio to be used in determining the distortion level), generating a computer implemented model for the test data, selecting a recommended operating point based on a computer implemented model, and determining compression parameters corresponding to the operating point. The compression parameters may subsequently be applied for configuration of compression applied to one or more production data sets that are similar to the test data. This abstract does not limit the scope of the invention as described in the claims.

Abstract: In one embodiment of the invention, a flash-based/solid-state storage system with an implemented data redundancy scheme such as RAID is configured to hold parity data in a volatile memory such as RAM and write such parity data to the non-volatile flash media when a full stripe of data has been written to the media. Other embodiments in certain situations force an early write of the parity for a partial stripe that has not been fully written to the non-volatile media. Those situations may include a data access error on data in a partial stripe and a detected power loss event with a partial stripe present. Embodiments are directed to writing additional data with the parity data for the partial stripe and then later using the additional data in data recovery. This approach allows the controller to easily detect the presence of a partial stripe and handle such a stripe accordingly.

Abstract: It is provided a computer comprising a nonvolatile memory for storing data, a control processor for controlling the saving of data into the nonvolatile memory, and a battery for supplying power to the computer in case of a failure of an external power supply, wherein the control processor checks a charge amount stored in the battery, calculates an amount of data which can be saved in the nonvolatile memory by the battery in case of a failure of the external power supply based on the checked charge amount, and saves data excluding the amount of data that can be saved, out of data which should be saved into the nonvolatile memory, into the nonvolatile memory in advance.

Abstract: Enabling remote debugging of virtual machines, in one aspect, may comprise attaching a debug virtual machine to a target virtual machine deployed in a virtualized environment. Interactions and/or access to the target virtual machine may be performed via the attached debug virtual machine. The debug virtual machine may be created and attached to the target virtual machine in response to receiving a request to debug the target machine, for example, from a remote user of the target virtual machine.

Abstract: Generally described, systems and methods are provided for detecting locations of failures of network paths. The system collects information from a plurality of nodes and links in a network, aggregates the collected performance information across paths in the network, processes the aggregated performance information for detecting failures on the paths, and determines at least one location for network failures. In some aspects, processing the aggregated information may include determining the performance information on each of the nodes and links in the network. The performance information on each of the nodes and links may be determined by application of a stochastic gradient descent (SGD) technique.

Abstract: A standby system device 200 which is connected to an active system device 100 includes a process information sharing unit 203B and a standby process management unit 203C. The process information sharing unit 203B receives active side process information indicating usage of resources of an active system process 103A operating on the active system device 100 from the active system device 100. The standby process management unit 203C terminates a standby process 203A before activating a takeover process 203D used for taking over processing of the active system process 103A when a takeover of the active system process is requested on the standby system device 200, the standby process 203A referring to the active side process information and acquiring resources in such a way that usage of resources of the standby process 203A is equal to or greater than the usage of resources of the active system process 103A.

Abstract: The present disclosure includes apparatus (e.g., computing systems, memory systems, controllers, etc.) and methods for providing data integrity. One or more methods can include, for example: receiving a number of sectors of data to be written to a number of memory devices; appending first metadata corresponding to the number of sectors and including first integrity data to the number of sectors, the first metadata has a particular format; generating second integrity data to be provided in second metadata, the second integrity data corresponding to at least one of the number of sectors (wherein the second metadata has a second format); and generating third integrity data to be provided in the second metadata, the third integrity data including error data corresponding to the second integrity data and the at least one of the number of sectors.

Abstract: Detecting failures of interconnected machines. A method includes establishing a machine to machine lease at a first machine using a first lease agent at the first machine to a second lease agent at a second machine as a result of an application on the first machine requesting to establish a lease with an application on the second machine. Using the machine to machine lease, the method further includes detecting a communication failure between the first machine and the second machine or a machine failure of the second machine.

Abstract: An apparatus for controlling a supply voltage to an electronic processing arrangement comprising a processor or a memory element, the apparatus being configured to receive an output of the electronic processing arrangement and comprising: error detection means for detecting errors in an output of the electronic processing arrangement; and means for adaptively varying the supply voltage to the electronic processing arrangement based on an analysis of errors detected in the output of the electronic processing arrangement. The apparatus may further comprise means for correcting errors detected in the output of the electronic processing arrangement.

Abstract: Connectivity fault notification is provided by generating an alarm indication signal at a device that is logically adjacent to the fault, and forwarding the alarm indication signal upward through various levels to at least one client level entity. The alarm indication signal may be suppressed at any level for a service instance if service is restored at that level, or if a protection path prevents disruption of the service instance at that level, or auto-suppressed at an originating node based on number of times transmitted or elapsed time. The alarm indication signal may include a point of failure indicator such as the MAC address of the device that generates the alarm indication signal, or a failed resource identity such as an IEEE 802.1AB LLDP MAC Service Access Point (“MSAP”). Further, the alarm indication signal may be employed to trigger use of the protection path.

Abstract: A method and a system are provided for determining an AMF configuration of a highly available system with respect to whether to failover or restart a component when the component fails. The AMF configuration specifies at least two service-units containing components that represent resources, and a set of service-instances representing workload incurred by provision of services using the resources. The method identifies a failover duration and a restart duration for each component in a service-unit; and determines a failover outage and a restart outage for each service-instance impacted by a failure of a given component, based on the failover duration and the restart duration of each component in the service-unit. The method further determines whether to failover or to restart the given component if the given component fails, based on the failover outage and the restart outage of each service-instance impacted by the failure of the given component.

Abstract: Error information is sent from a terminal adaptor that accesses a wireless network to terminal equipment coupled to access the wireless network through the terminal adaptor. The error information is sent in response to existence of any one of a plurality of errors conditions with respect to access to the wireless network. The error information includes an error type identifying a domain associated with a source of the error condition being reported and an error code providing a reject error cause for the error condition. One of the error conditions may include an unsolicited error received by the terminal adaptor from the wireless network or when a request by the TA is ignored by the wireless network.

Abstract: Embodiments of the invention are directed to providing detailed error reporting of data operations performed on a NVM storage device. In one embodiment, a controller interfaces with a NVM storage device including NVM storage coupled with a bridge. In one embodiment, the controller is provided physical, page-level access to the NVM via the bridge, and the bridge provides detailed error reporting of the data operations that the bridge performs on the NVM on behalf of the controller. For example, the bridge may provide page level reporting indicating which page(s) failed during a read operation. Detailed error reporting allows the controller to better understand the failures that occurred in a data access operation in the NVM. It also enables the controller to manage the flash media at the physical page/block level. In one embodiment, detailed error reporting also enables the return of discontinuous ranges of data with the error portions removed.

Abstract: Systems and methods which provide mount catalogs to facilitate rapid volume mount are shown. A mount catalog of embodiments may be provided for each aggregate containing volumes to be mounted by a takeover node of a storage system. The mount catalog may comprise a direct storage level, such as a DBN level, based mount catalog. Such mount catalogs may be maintained in a reserved portion of the storage devices containing a corresponding aggregate and volumes, wherein the storage device reserved portion is known to a takeover node. In operation according to embodiments, a HA pair takeover node uses a mount catalog to access the blocks used to mount volumes of a HA pair partner node prior to a final determination that the partner node is in fact a failed node and prior to onlining the aggregate containing the volumes.

Abstract: Mechanism for consistent core hang detection on a processor with multiple processor cores, each having one or more instruction execution pipelines. Each core may also include a hang detection unit with a counter unit that may generate a count value based on a clock source having a frequency that is independent of a frequency of a processor core clock. The hang detection unit may also include a detector logic unit that may determine whether a given instruction execution pipeline has ceased processing a given instruction based upon a state of the processor core and whether or not the given instruction has completed execution prior to the count value exceeding a predetermined value.