Abstract: An exercise information acquisition equipment of the present invention is an electronic equipment which builds therein a battery, is driven with electric power of the battery and acquires information relating to an exercise that a user performs and includes a battery remaining amount acquisition device which acquires a battery remaining amount of the battery, a time information acquisition device which acquires information relating to a time taken for the exercise which is information that how long the user plans to perform the exercise and an electric power control device which controls an operation pertaining to a power consumption reduction of the electronic equipment on the basis of the battery remaining amount and the information relating to the time taken for the exercise.

Abstract: Device verification extension technology obtains, in response to a request to verify a signature associated with first data, an asymmetric verifier application from off-device storage. The asymmetric verifier application is loaded and executed. The signature associated with the first data is verified using the asymmetric verifier application using asymmetric-key cryptography.

Abstract: A power management technique for a printer includes detecting a change in a state of operation of a printing device. The amount of power available to operate all functions of the printing device is calculated. Next, power is delivered to specified functions of the printing device based on the calculated amount of power available, wherein the specified functions are a subset of all functions of the printing device. Then, it is determined whether the specified functions operate correctly.

Abstract: Reducing power consumption at an information handling system (IHS), including identifying a first data set associated with a first application, and a second data set associated with a second application; storing the first data set at a first physical storage device, and storing the second data set at a second physical storage device; reducing a power consumption of a storage device system, including: determining that the first and second applications are out-of-focus with respect to an operating system (OS) of the IHS, and in response, maintaining a low power state of the first and the second physical storage devices; detecting that the first application is in-focus with respect to the OS of the IHS, and in response, adjusting a power state of the first physical storage device from the low power state to an active power state while maintaining the low power state of the second physical storage device.

Abstract: An electronic device includes a semiconductor memory device configured to store process information and to output the process information to the outside; and a host configured to read the process information from the semiconductor memory device, and to select one of a plurality of operation modes depending on the process information so as to be set to an operation mode of the semiconductor memory device. The plurality of operation modes may define one or more of power consumption of the semiconductor memory device or a response characteristic of the semiconductor memory device.

Abstract: An information handling system may include a host system comprising a host system processor and a management controller communicatively coupled to the host system processor and configured to perform out-of-band management of a plurality of devices of the information handling system, and further configured to, during a powering on of the host system randomly select a subset of one or more devices of the plurality of devices for partial validation of firmware of the plurality of devices, randomly select a plurality of offsets associated with the one or more devices for partial verification of the firmware, and perform verification of the one or more devices at the plurality of offsets.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to improve computing device power management. An example apparatus includes a usage classifier to classify usage of a computing system, a low battery probability determiner to determine a probability of the computing system operating with a low battery capacity based on the classification, a policy reward determiner to determine an adjustment of a policy based on at least one of the classification or the probability, and determine a battery capacity of the computing system in response to the adjustment, and a policy adjustor to adjust the policy in response to the battery capacity satisfying a threshold.

Abstract: Certain aspects of the disclosure are directed toward validation and installation of a file system. A method for mitigating security breach for a circuit platform subject to compromise by unauthorized changes to a file system includes abstracting the file system into an encrypted file with cryptographically signed components. The file system may have instruction code or other data for an operating system and may be stored by or on behalf of the circuit platform. During boot time of the operating system, an unencrypted version of the operating system and the encrypted file may be accessed and used by validating a signature associated with the file system. In response to validating the signature, the file system is installed into a transient, non-persistent storage circuit. As such, the operating system executes instruction code via a central processing unit (CPU) circuit under authorization based on the validated signature.

Abstract: An electronic device is provided. The electronic device includes an operation of determining at least one control level by executing at least one scheduling process, an operation of selecting one control level from among the at least one control level, and an operation of transmitting a power control signal corresponding to the selected control level to one or more control target devices. The operation of determining the control level may include an operation of performing a first scheduling process of receiving first power usage data from an external power amount data providing device and determining a first control level based on the first power usage data. In addition to this, various embodiments identified through the specification are possible.

Abstract: A pulse counting apparatus operating at a low power and an operation method thereof are provided. The pulse counting apparatus includes a pulse counter configured to count a number of pulses inputted from outside of the pulse counting apparatus and generate an interrupt signal; a timer unit configured to generate a wake-up signal according to a preset time; a real time clock (RTC) configured to serve as a clock of the pulse counter and the timer unit; and a processor configured to switch from a sleep mode to an active mode when the interrupt signal or the wake-up signal is generated.

Abstract: An electronic apparatus and a power management method thereof are provided. The power management method is adapted to the electronic apparatus and includes the following steps. A target time is obtained according to a user input. A remaining demand time is determined according to the target time and an elapsed time after activating timing. A time-to-empty of a battery device is obtained. The time-to-empty of the battery device and the remaining demand time are compared to provide a visual notification and a user behavior suggestion message according to the comparison result. The user behavior suggestion message includes at least one power saving operation.

Abstract: In one embodiment, a system includes power management control that controls a duty cycle of a processor to manage power. The duty cycle may be the amount of time that the processor is powered on as a percentage of the total time. By frequently powering up and powering down the processor during a period of time, the power consumption of the processor may be controlled while providing the perception that the processor is continuously available. For example, the processor may be a graphics processing unit (GPU), and the period of time over which the duty cycle is managed may be a frame to be displayed on the display screen viewed by a user of the system.

Abstract: Disclosed are a method and apparatus for controlling a hardware module, electronic device and storage medium. In an embodiment of the present disclosure, the method may include: timing a waiting state of the hardware module to obtain a current waiting duration of the hardware module when it enters a first waiting state; generating an interrupt signal based on the current waiting duration; determining program information corresponding to the current waiting duration under triggering from the interrupt signal; executing an action corresponding to the program information for the hardware module, and controlling it to enter a second waiting state. In the present disclosure, the hardware module is controlled to execute actions corresponding to different programs based on different waiting durations through an interrupt mechanism, thus controlling the hardware module to switch between waiting states with different power consumption, and achieving a good balance between energy saving and performance.

Abstract: Bandwidth for information transfers between devices is dynamically changed to accommodate transitions between power modes employed in a system. The bandwidth is changed by selectively enabling and disabling individual control links and data links that carry the information. During a highest bandwidth mode for the system, all of the data and control links are enabled to provide maximum information throughout. During one or more lower bandwidth modes for the system, at least one data link and/or at least one control link is disabled to reduce the power consumption of the devices. At least one data link and at least one control link remain enabled during each low bandwidth mode. For these links, the same signaling rate is used for both bandwidth modes to reduce latency that would otherwise be caused by changing signaling rates. Also, calibration information is generated for disabled links so that these links may be quickly brought back into service.

Abstract: A mission elapsed time (MET) unit for using during outer space missions. The MET unit comprises a MET core, a crystal oscillator (XO) operably connected to the MET core, an external pulse per second (XPPS) source generating an XPPS input signal and operably connected to the MET core, a synchronization logic and a “Blackout Limit” register. Both the synchronization logic and the “Blackout Limit” register are arranged between the XPPS source and the MET core so that each of the synchronization logic and the “Blackout Limit” register is operably connected to both the XPPS source and the MET core. The MET core includes a sub-seconds counter keeping track of time over scales of less than one second and a seconds counter keeping track of time over scales of larger than one second.

Abstract: An apparatus and method to protect unauthorized change to a reference clock for a processor. The apparatus comprises: a first oscillator to generate a first clock; a second oscillator to generate a second clock; a third oscillator to generate a third clock; a first counter to count frequency of the first clock with respect to a fourth clock; a second counter to count frequency of the second clock with respect to the fourth clock; a third counter to count frequency of the third clock with respect to the fourth clock; and a circuitry to compare frequencies of the first, second, and third clocks with one another. The oscillators can be embedded in an interposer or package. These oscillators include one or more of: LC oscillator, micro electro-mechanical system (MEMs) based resonator, or ring oscillator.

Abstract: A power supply architecture combines the benefits of a traditional single stage power delivery, when there are no additional power losses in the integrated VR with low VID and low CPU losses of FIVR (fully integrated voltage regulator) and D-LVR (digital linear voltage regulator). The D-LVR is not in series with the main power flow, but in parallel. By placing the digital-LVR in parallel to a primary VR (e.g., motherboard VR), the CPU VID is lowered and the processor core power consumption is lowered. The power supply architecture reduces the guard band for input power supply level, thereby reducing the overall power consumption because the motherboard VR specifications can be relaxed, saving cost and power. The power supply architecture drastically increases the CPU performance at a small extra cost for the silicon and low complexity of tuning.

Abstract: According to an embodiment of the disclosure, an electronic device includes a processor and a memory operationally connected to the processor and configured to store instructions that, when executed by the processor, cause the processor to configure a time period comprising multiple unit durations, check for utilization of the processor for each of the multiple unit durations of the time period, collect at least one variation of the utilization of the processor based on the utilization of the processor for each of the multiple unit durations, acquire a temporal probability density function based on the at least one collected variation, determine a probability density function corresponding to the temporal probability density function based on a previously stored probability density function table, and determine an operating frequency for a next unit duration based on at least part of the identified probability density function. Various other embodiments are possible.

Abstract: A circuit system comprises a processor, a first clock with a first frequency, a second clock with a second frequency, such second frequency being higher than said first frequency and a clock calibration module. The clock calibration module comprises a plurality of counters configured to count cycles of the second clock when triggered. Each of the plurality of counters is configured to be triggered at successive cycles of the first clock. Each of the plurality of counters is configured, after a predetermined number of cycles of the first clock, to output a count of elapsed second clock cycles and the processor is configured to determine, using the counts outputted by the plurality of counters, a ratio between the first frequency and the second frequency.

Abstract: A power supply having at least one PMIC provides flexible control to the power manage systems. The PMIC has an enable pin configured to receive a control signal, and a clock pin configured to generate and/or receive a series of clock pulses, so as to facilitate the operation of the PMIC.