Abstract: In the present invention, control feasibility in a vehicle control system architecture is efficiently determined by performing determination based on control feasibility in a physical element based on a converted parameter when a logical architecture is arranged in a physical architecture. The present invention includes: an arrangement unit 101 that arranges a logical architecture 601, which includes a linkage of each of logical functions and an execution time constraint of the linkage, in a physical architecture 300; a delay time calculation unit 104 that calculates a processing delay time based on a converted parameter when the logical architecture 601 is arranged in the physical architecture 300; and a verification unit 102 that verifies whether a total of the processing delay time satisfies the execution time constraint.

Abstract: In one embodiment, a processor includes a plurality of intellectual property (IP) circuits, each to execute instructions and including a local control circuit to enable the IP circuit to operate at a level above a local current budget for the IP circuit, unless the processor is undergoing a global violation. The processor may further include a power controller coupled to the plurality of IP circuits. The power controller may include a control circuit to receive request information from the plurality of IP circuits and, based at least in part on the request information, determine that the processor is undergoing the global violation when a global current budget is exceeded. Other embodiments are described and claimed.

Abstract: A computing device that implements a multithread parallel processing computing platform prior to initialization of system memory is provided. To implement this platform, the computing device executes enhanced firmware that defines a plurality of application processors (APs) under the control of a boot-strap processor (BSP). The BSP preserves backward compatibility of the APs by configuring cross-reference circuitry (e.g., a programmable attribute map) to reroute memory access requests generated by the APs that are addressed to a wakeup buffer to a redirected memory address. Memory at the redirected memory address stores AP initialization instructions and instructions to retrieve and process early stage process instructions stored elsewhere (e.g., in fast access cache memory). The APs, in parallel, execute the initialization instructions and the early stage process instructions stored in cache to complete an early stage process, such as memory training.

Abstract: A heat dissipation apparatus with energy-saving effect is coupled to an operation unit, and the heat dissipation apparatus includes a control unit and a drive circuit. The control unit determines whether the operation unit enters an energy-saving mode according to a first signal provided by the operation unit. The control unit shields a plurality of second signals provided to the drive circuit according to the energy-saving mode. The drive circuit does not drive the heat dissipation unit and the heat dissipation unit enters an inertia deceleration.

Abstract: A system for consistently implementing reset and power management of IP agents on a System on a Chip (SoC). When IP agents undergo a reset, an individual negotiation takes placed between an interconnect and each IP agent over a link. Each IP agent can emerge from reset at its own time schedule, independently of the timing of the other IP agents. The interconnect may be configured as a proxy for any IP agent that is inoperable, including prior to reset, when in a power-down mode, or malfunctioning.

Abstract: A method of operating an electronic device according to various embodiments r may include executing an application, identifying at least one genetic element corresponding to an attribute related to genetic information of a user with respect to the application, determining a setting value for the attribute based on the at least one genetic element, and providing a service related to the application based on the determined setting value.

Abstract: An information processing apparatus including a volatile storage unit, and is operated in any of a plurality of modes including a first power mode and a second power mode, power being supplied to the storage unit in the first power mode and the second power mode, power consumption in the first power mode being higher than power consumption in the second power mode.

Abstract: A system includes a memory device and a power disable circuit coupled to a bus connector and to power circuitry adapted to power on and off the memory device. A processing device is coupled to the bus connector, to the power disable circuit, and to the memory device. The processing device is to monitor a state of a power disable (PWDIS) signal of the bus connector while the PWDIS signal is at a first voltage level, and in response to the PWDIS signal transitioning to a second voltage level, determine whether a length of time for which the PWDIS signal has been at the second voltage level satisfies a threshold criterion. In response to the length of time for which the PWDIS signal has been at the second voltage level satisfying the threshold criterion, the processing device is to enable the power disable circuit with a general purpose input/output signal.

Abstract: Systems and methods are disclosed for scheduling component activation. A computer-implemented method may include: detecting a first status of a head-mounted device with one or more physical computer processors; after a first time interval since detecting the first status, disabling a Wi-Fi component of the head-mounted device for a second time interval with the one or more physical computer processors; and after the second time interval, activating the Wi-Fi component for a third time interval with the one or more physical computer processors.

Abstract: A method may include, in a system comprising a plurality of power supply units, determining a redundancy configuration of the plurality of power supply units, determining a power capacity of the plurality of power supply units, determining a number of modular information handling systems installed in the system, determining a chassis-level maximum transient power limit for each of the modular information handling systems based on the redundancy configuration, the power capacity, and the number of modular information handling systems, determining a chassis-level maximum average power limit for each of the modular information handling systems, and communicating the chassis-level maximum transient power limit and chassis-level maximum average power limit to a respective baseboard management controller of each of the modular information handling systems, wherein each respective baseboard management controller is configured to determine if sled-level power requirements of its respective information handling system

Abstract: Devices and techniques for arbitrating operation of memory devices in a managed NAND memory system to conform the operation to a power budget. In an example, a method can include receiving an operation change indication for a NAND memory operation at power management circuitry of a NAND memory system, and summing a power credit to a value of a first register associated with the operation change indication to provide an indication of instantaneous power consumption of the NAND memory system as the value of the first register.

Abstract: An electronic device is provided that includes a base, a processor, and a tablet having a front surface, a rear surface and a bottom edge surface. A processor may operate at a first operating condition when the tablet is coupled to the base, and the processor may operate at a second operating condition when the tablet is not coupled to the base. The tablet may include a heat conducting device and an active edge. The heat conducting device may conduct heat from the processor to the active edge where the heat may be dissipated using supplemental cooling.

Abstract: There is provided a method of operating a computing device including a processing component based on power consumption. The method includes: obtaining power mode information about the processing component, measuring a temperature of the processing component and a current that flows through the processing component in response to the obtaining the power mode information, generating leakage power information based on the power mode information and the measured temperature and current, and storing the generated leakage power information in a memory.

Abstract: A system for securely and reliably transferring startup script files over a network may include a unified extensible firmware interface (UEFI) network stack on a client server wherein the client server requests startup script over the network upon startup of the client server using a secure transfer network protocol and receives over the network the startup script. A computing device may comprise a unified extensible firmware interface (UEFI) shell to request a download of startup script, over a network, upon startup of the client server wherein the startup script is staged in a provisioned storage device within the client server to be mounted as local file systems in the client server. The UEFI shell.

Abstract: A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.

Abstract: In one embodiment, a processor includes a non-volatile storage to store a plurality of configurations for the processor, the non-volatile storage including a plurality of entries to store configuration information for the processor for one of the plurality of configurations, the configuration information including at least one of a guaranteed operating frequency and a core count, at least one of the entries to store the core count. The processor further includes a power controller to control the processor to operate at one of the plurality of configurations based at least in part on a selected thermal set point of a plurality of thermal set points of the processor, each of the plurality of thermal set points associated with one of the configurations. Other embodiments are described and claimed.

Abstract: A method for updating a power mode parameter combination, includes identifying a current hardware combination of a client host; loading and executing a current application program; loading a default profile according to the current application program to update a current power mode parameter combination of the current hardware combination; receiving a user-defined parameter combination to update the current power mode parameter combination of the current hardware combination; correlating the current application program, the current hardware combination and the updated current power mode parameter combination to generate a current profile as an updated default profile; and transmitting the current profile to a server as a candidate profile.

Abstract: In a method of operating a system-on-chip (SOC), the SOC includes a plurality of processor cores. An operating frequency of the plurality of processor cores is set to a first operating frequency based on permitted power consumption of the SOC and an operating status of the plurality of processor cores. The first operating frequency is within a maximum operating frequency of the plurality of processor cores. At least one of the plurality of processor cores performs at least one processing operation based on the first operating frequency. When present power consumption of the SOC is determined as exceeding the permitted power consumption, a warning signal is activated, and a first control operation for reducing the present power consumption is performed immediately thereafter.

Abstract: An information handling system includes first and second power supplies and a power assist unit. The power supplies are each configured to provide power to a power rail to power a load of the information handling system, to provide input power indications that indicates whether or not the power supplies are receiving good input power, and to provide a output power indications that indicates whether or not the power supplies are providing good power to the power rail. The power assist unit is coupled to the power rail and includes a power storage element, a converter coupled to the power storage element and to the power rail, and a controller. The controller receives a hold-up signal from the information handling system, and in response to receiving the hold-up signal, directs the converter to provide power from the power storage element to the power rail. The hold-up signal is based upon the input power indications and upon the output power indications.

Abstract: Control of power supplied to a machine intelligence (MI) processor is provided with an energy reservoir and power switching circuitry coupled to a power supply, the energy reservoir, and to power delivery circuitry of the MI processor. Control circuitry directs the power switching circuitry to charge the energy reservoir from the power supply or discharge the energy reservoir to the MI processor based on MI state information obtained from the MI processor. Processes for charging and discharging such an energy reservoir are provided. Processes for analyzing state information of the MI processor and configuring the control circuitry are also provided.