Abstract: The present invention discloses a method for low power power-on processing, the method comprising: when a terminal receives a power-on event in a low power power-off state, triggering a system to start according to the power-on event, wherein a battery voltage in the low power power-off state is less than or equal to a power-off voltage and is greater than or equal to a system starting voltage; and after the system is started, presenting a low power prompt via a screen.

Abstract: An electronic device is provided that includes a base, a processor, and a tablet having a front surface, a rear surface and a bottom edge surface. A processor may operate at a first operating condition when the tablet is coupled to the base, and the processor may operate at a second operating condition when the tablet is not coupled to the base. The tablet may include a heat conducting device and an active edge. The heat conducting device may conduct heat from the processor to the active edge where the heat may be dissipated using supplemental cooling.

Abstract: Bandwidth for information transfers between devices is dynamically changed to accommodate transitions between power modes employed in a system. The bandwidth is changed by selectively enabling and disabling individual control links and data links that carry the information. During a highest bandwidth mode for the system, all of the data and control links are enabled to provide maximum information throughout. During one or more lower bandwidth modes for the system, at least one data link and/or at least one control link is disabled to reduce the power consumption of the devices. At least one data link and at least one control link remain enabled during each low bandwidth mode. For these links, the same signaling rate is used for both bandwidth modes to reduce latency that would otherwise be caused by changing signaling rates. Also, calibration information is generated for disabled links so that these links may be quickly brought back into service.

Abstract: Method and system are provided for power socket management. The method carried out at a server may include receiving power data from a plurality of user devices and obtaining event information for an event location, including details of the user devices required for the event. The method may process the power data for the required user devices for an event by optimizing the use of power sockets at the event location. The method may notify the required user devices of the optimized socket usage for a user device.

Abstract: A control method of a portable electronic device (PED) includes following steps. A trigger event is received. Next, an accelerator detects a first behavior of the PED and produces a first signal. If the first signal satisfies a first preset condition, the accelerator detects a second behavior of the PED and produces a second signal. If the second signal satisfies a second preset condition, the PED performs an action.

Abstract: A system with a local data collector that collects power management data for a subsystem. The local data collector can determine whether a first formatting associated with a first channel between the local data collector and a system power management data collector is equivalent to a second formatting associated with a second channel between the local data collector and the system power management data collector, and in response to a determination that the first formatting and second formatting are not equivalent format the power management data according to the first formatting; store the power management data formatted according to the first formatting in a first location in a memory; format the power management data according to the second formatting; and store the power management data formatted according to the second formatting in a second location the memory.

Abstract: An information processing apparatus capable of changing a state of power supply to respective parts of the apparatus with less user operation. When a sleep recovery button is depressed in a power saving mode, a button depression time is measured, and whether a length of the measure depression time exceeds a threshold value is determined. If the depression time exceeds the threshold value, a normal power mode is selected as power mode after transition. If the depression time does not exceed the threshold value, another power saving mode is selected as power mode after transition. According to the selected power mode, a state of power supply to respective parts of the apparatus is changed.

Abstract: A charge level for a first rechargeable power source, a second rechargeable power source, and a third rechargeable power source is determined. The first rechargeable power source is determined to be below a threshold level of charge. In response to determining that the first rechargeable power source is below a threshold level of charge, a switch is made from the first rechargeable power source to the second rechargeable power source.

Abstract: A dynamic voltage frequency scaling (DVFS) system is provided. The DVFS system includes: a computation unit, a power management unit (PMU), a hardware activity monitor (HAM), and a hardware voltage monitor (HVM). The HAM monitors a working status and temperature information of the computation unit, and determines whether to update an operating voltage and frequency of the computation unit according to the working status, the temperature information, and a previous determination result. When the HAM determines to update the operating voltage and frequency, the HAM generates a first control signal to the PMU to calibrate the operating voltage and frequency. The HVM detects timing information of the computation unit and determine whether to fine-tune the operating voltage according to the detected timing information. When the HVM determines to fine-tune the operating voltage, the hardware monitor generates a second control signal to the PMU to fine-tune the operating voltage.

Abstract: A computer-implemented method for command-address-control calibration of a memory device includes starting, via a processor, a controller clock for the memory device, releasing, via the processor, a reset on the memory device, running, via the processor, a calibration pattern for calibrating the memory device by placing the memory device in calibration mode, where the calibration pattern is initiated prior to an initialization of the memory device, calibrating, via the processor, the memory device with a calibration setting based on the calibration pattern, and initializing the memory device based on the calibration setting.

Abstract: An electronic device (20) has a clock path (24) for propagating a clock signal and a clock propagating element (26) on the clock path. An analogue element (30) coupled to the clock path (24) varies, in dependence on an analogue level of a first signal (32), a switching delay for the clock propagating element (26) to trigger a transition of the clock signal. The first signal is a digitally sampled signal. This provides a mechanism for providing a fast reduction in clock frequency even if the first signal is a metastable signal, which is useful for avoiding errors causes by voltage drops.

Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

Abstract: Certain aspects direct to systems and methods for performing scheduled power mode switch for thin client computing device. The system includes a server a computing device. The server receives a plurality of inputs, generates, based on the inputs, a power mode switch schedule including at least one sleep time and at least one wake time, and controls at least one computing device functions as a thin client to update configuration data of the at least one computing device with the power mode switch schedule and to switch between the wake mode the sleep mode according to the updated configuration data.

Abstract: The present disclosure provides devices and techniques for managing power distribution in a device. The devices and techniques include determining a first power level of a first battery of the device, and determining a second power level of a second battery of the device. Also, the devices and techniques include adjusting an input current limit of a system charger based on the first power level and the second power level. Additionally, the devices and techniques include steering power from one or both of the first battery or the second battery to at least one processor of the device based on the input current limit.

Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a management device. The management device executes a first bootloader from a first image stored at a primary storage device of the management device. The management device re-executes the first bootloader from the first image when the executing is not successful and a number of re-execution is less than a predetermined number. The management device locates a second image from a secondary storage device when the execution of the first bootloader is not successful and the number of re-execution is greater than or equal to the predetermined number. The management device executes a second bootloader from the second image subsequent to the locating the second image.

Abstract: The amount of drift in an oscillator, as a function of temperature, can be profiled by adjusting the temperature and monitoring the corresponding change in frequency of the oscillator. Temperature sensors on a computing device can provide the temperature readings for the profiling, as well as readings during operation. A system clock on the computing device can be synchronized with a reliable external clock at a regular interval, such as every fifteen minutes. Between those synchronizations, the temperature values provided by the temperature sensors can be determined and the corresponding oscillator drift determined according to the oscillator profile. The drift value can be used to adjust the output of the system clock to account for variations that may become present between the synchronization times. Effects of factors such as voltage and humidity can also be profiled to provide a more accurate timing signal.

Abstract: A technique involves performing, in a data storage system, a full-boot procedure which includes a set of critical boot activities and a set of avoidable boot activities. The technique further involves providing, in response to completion of the full-boot procedure, a fastboot notification indicating to the data storage system that a fastboot procedure is to be performed in response to a warm boot event. The technique further involves placing, after providing the fastboot notification, the data storage system into a normal operating mode in which the data storage system performs data storage operations in response to data storage requests from a set of external host computers. Such operation enables the data storage system to subsequently perform a fastboot procedure that avoids the set of avoidable boot activities in response to the next warm boot event.

Abstract: In one example embodiment, an integrated circuit includes a memory configured to store a first table listing a plurality of clip frequencies respectively corresponding to a plurality of reference temperatures, and a second table listing one or more of the plurality of clip frequencies and a plurality of timestamps each respectively corresponding to the one or more of the plurality of clip frequencies. The integrated circuit further includes a cooling frequency adjustor configured to select one of the plurality of clip frequencies stored in the first table as a first clip frequency, and store a current timestamp of the first clip frequency in the second table. The integrated circuit further includes a central processing unit (CPU) configured to control an operation of the cooling frequency adjustor.

Abstract: Scheduling memory accesses in a memory system having a multiple ranks of memory, at most r ranks of which may be powered up concurrently, in which r is less than the number of ranks. If fewer than r ranks are powered up, a subset of requested powered down ranks is powered up, such that at r ranks are powered up, the subset of requested powered down ranks to be powered up including the most frequently accessed requested powered down ranks. Then, if fewer than r ranks are powered up, a subset of unrequested powered down ranks is powered up, such that a total of at most r ranks is powered up concurrently, the subset of unrequested powered down ranks to be powered up including the most frequently accessed unrequested powered down ranks.

Abstract: In programmable equipment where it is either undesirable or impractical to construct the program code with embedded licensing decision points, the program is constructed by hard-coding the license rights into the program code at program build time. License permissions are obtained from a sales order system and used to produce a code image, or select a pre-existing, pre-validated code image which contains only those features, facilities, or capabilities allowed by the applicable license rights for that particular sales order and on that particular programmable unit. Functionality of the device is updated as appropriate by use of a bootloader on the device for installation of a firmware image. In this way, the invention overcomes the technical limitations inherent in such devices by reprogramming the device to alter device functionality in keeping with rights and privileges added or deleted therefrom with regard to software installed thereon.