Abstract: A control method of a portable electronic device (PED) includes following steps. A trigger event is received. Next, an accelerator detects a first behavior of the PED and produces a first signal. If the first signal satisfies a first preset condition, the accelerator detects a second behavior of the PED and produces a second signal. If the second signal satisfies a second preset condition, the PED performs an action.

Abstract: In accordance with a first aspect of the present disclosure, a transponder is provided, comprising: digital logic for processing one or more portions of a data frame; a status detection unit configured to detect a status of a data frame reception or data frame transmission; a clock gating unit configured to apply clock gating to said digital logic in dependence on the status of said data frame reception or data frame transmission. In accordance with further aspects of the present disclosure, a corresponding method of operating a transponder is conceived, and a corresponding computer program is provided.

Abstract: An embodiment of a semiconductor package apparatus may include technology to determine if a wake event corresponds to a zero-power state of a computer operating system, determine if a run-time state is valid to wake the operating system from the zero-power state, and wake the operating system from the zero-power state to the run-time state if the run-time state is determined to be valid. Other embodiments are disclosed and claimed.

Abstract: A technique for fine-granularity speed binning for a processing device is provided. The processing device includes a plurality of clock domains, each of which may be clocked with independent clock signals. The clock frequency at which a particular clock domain may operate is determined based on the longest propagation delay between clocked elements in that particular clock domain. The processing device includes measurement circuits for each clock domain that measure such propagation delay. The measurement circuits are replica propagation delay paths of actual circuit elements within each particular clock domain. A speed bin for each clock domain is determined based on the propagation delay measured for the measurement circuits for a particular clock domain. Specifically, a speed bin is chosen that is associated with the fastest clock speed whose clock period is longer than the slowest propagation delay measured for the measurement circuit for the clock domain.

Abstract: Systems and methods for providing power to a home entertainment integrated circuit chip are disclosed. The home entertainment integrated circuit chip can operate in at least two power control modes: “power on” mode and “standby” mode. In power on mode, power is supplied to IC core module from a main power supply. The power supplied to the IC core module is isolated from power supplied to a standby island. Accordingly, during the second mode power is applied only to the standby power island through a regulator internal to the integrated circuit chip. The regulator is coupled to an external peripheral input/output (I/O) power supply that is independent of the main power supply.

Abstract: In one embodiment, a system includes power management control that controls a duty cycle of a processor to manage power. The duty cycle may be the amount of time that the processor is powered on as a percentage of the total time. By frequently powering up and powering down the processor during a period of time, the power consumption of the processor may be controlled while providing the perception that the processor is continuously available. For example, the processor may be a graphics processing unit (GPU), and the period of time over which the duty cycle is managed may be a frame to be displayed on the display screen viewed by a user of the system.

Abstract: A universal serial bus (USB) hub includes detection circuits for a D? and a D+ connection of a USB port and a control circuit. The control circuit is configured to disable, detection circuits, respective impedances. After disabling the respective impedances, the USB hub is further configured to detect, at the detection circuits, respective values from the D+ connection and the D? connection. The USB hub is further configured to, based upon the respective values, switch the USB port between a device port configuration and a host port configuration.

Abstract: A control method of a memory storage device is provided and includes: detecting a first signal stream controlled by a host system; executing a boot code according to the first signal stream and entering a boot code mode; and receiving a command from the host system in the boot code mode and not executing a firmware code stored in a rewritable non-volatile memory module in the memory storage device. According, operational flexibility of the memory storage device may be enhanced.

Abstract: An electronic device includes a power supply, a connector, a detector, and a switch. The connector is configured to be alternatively connectable in a first direction and in a second direction. The detector is configured to detect which of the first direction and the second direction the connector has been connected in. The switch is configured to switch a state of the electronic device between a first state to supply power to another device and to a second state to receive power from said another device. The switch is configured to switch the state of the electronic device to the first state or the second state according to a connection direction of the connector detected by the detector.

Abstract: Operations include restoring a trusted system firmware state. A system stores a set of self-contained secure code in a secure code store. The system stores a set of operational code in an operational code store. The system executes the secure code or the operational code upon system start up, depending whether the system is configured in a secure mode, or in a normal operational mode. When the system is configured in secure mode, the system executes the secure code. In secure mode, the system also overwrites a current version of the operational code stored in the operational code store with a replacement version of the operational code referenced by the secure code. When the system is configured in normal operational mode, the system executes the operational code. During normal operation, the secure code store is electrically isolated.

Abstract: An apparatus includes a processor, USB connectors, and variable resistors or variable current sources. The processor is configured to read and load instructions causing the processor to dynamically adjust a current consumed by a given connector through adjustment of a related variable resistor or variable current source.

Abstract: The invention relates to a computer comprising: a plurality of processing units each having instruction storage holding a local program, an execution unit executing the local program, data storage for holding data; an input interface with a set of input wires, and an output interface with a set of output wires; a switching fabric connected to each of the processing units by the respective set of output wires and connectable to each of the processing units by the respective input wires via switching circuitry controllable by each processing unit; a synchronisation module operable to generate a synchronisation signal to control the computer to switch between a compute phase and an exchange phase, wherein the processing units are configured to execute their local programs according to a common clock, the local programs being such that in the exchange phase at least one processing unit executes a send instruction from its local program to transmit at a transmit time a data packet onto its output set of connection

Abstract: Example implementations relate to memory mode categorization. An example boot process modification can include invoking a first service of a client operating system (OS) on top of an enabled host OS, modifying a boot process of the host OS using the first service, and executing applications within the client OS based on the modified boot process of the host OS.

Abstract: Systems and methods are disclosed for phase locking multiple clocks of different frequencies. In certain embodiments, an apparatus may be configured to downsample a first clock having a first frequency and a second clock having a second frequency into downsampled clocks having the same frequency. The apparatus may adjust a frequency of the second clock so that the downsampled clocks are phase aligned. The apparatus may reset counters of the divider circuits that perform the downsampling so align them to a counter for the first clock. A counter for the second clock may also be reset to align with the counter for the first clock. The synchronized clocks may be applied in data storage operations, such as self-servo writing operations, where the first clock may be a read clock and the second clock may be a write clock.

Abstract: The invention relates to a computer comprising: a plurality of processing units each having instruction storage holding a local program, an execution unit executing the local program, data storage for holding data; an input interface with a set of input wires, and an output interface with a set of output wires; a switching fabric connected to each of the processing units by the respective set of output wires and connectable to each of the processing units by the respective input wires via switching circuitry controllable by each processing unit; a synchronisation module operable to generate a synchronisation signal to control the computer to switch between a compute phase and an exchange phase, wherein the processing units are configured to execute their local programs according to a common clock, the local programs being such that in the exchange phase at least one processing unit executes a send instruction from its local program to transmit at a transmit time a data packet onto its output set of connection

Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

Abstract: A fiber optic-based communications network includes: a power insertion device, connected to multiple fiber links from a data source, configured to provide power insertion to a hybrid fiber/power cable connected to at least one fiber link of the multiple fiber links; the hybrid fiber/power cable, connecting the power insertion device to a connection interface device, configured to transmit data and power from the power insertion device to the connection interface device; and the connection interface device, configured to provide an interface for connection to an end device via a power over Ethernet (PoE)-compatible connection and to provide optical to electrical media conversion for data transmitted from the power insertion device to an end device via the hybrid fiber/power cable and the PoE-compatible connection.

Abstract: Concepts and technologies are disclosed herein for providing and using an accessory setting service. Accessory data can be received from a computing device in communication with an accessory. The accessory data can include a unique identifier associated with the accessory. Based upon the unique identifier, a determination can be made as to whether or not the accessory data relates to a new accessory. If the accessory data does not relate to a new accessory, settings data associated with the accessory can be generated and transmitted to a recipient. If the accessory data relates to the new accessory, accessory settings associated with the accessory can be identified and stored with the unique identifier as accessory settings data.

Abstract: A device boots in a secure manner that allows measurements reflecting which components are loaded during booting to be generated. Measurements of such components, as well as of a device management agent and the security state of the device, are also obtained. The device management agent accesses an attestation service for an enterprise, which is a collection of resources managed by a management service. The device management agent provides the obtained measurements to the attestation service, which evaluates the measurements and based on the evaluation determines whether the device is verified for use in the enterprise. The management service uses this verification to ensure that the device management agent is running in a secure manner, is accurately providing indications of the state of the device to the management service, and is implementing policy received from the management service.

Abstract: Embodiments are disclosed for methods and systems for selectively initializing elements of an operating system of a computing device. In some embodiments, a method of selectively loading hardware instances for a computing device includes receiving a notification identifying a driver for a hardware instance, initializing the driver identified in the notification, and for each hardware instance supported by the driver, determining if that hardware instance is associated with a first stage of initialization. The method may further include initializing the identified hardware instance and each other hardware instance supported by the driver that is associated with a first stage of initialization.