Abstract: The present invention relates to a monitor wafer measuring method and measuring apparatus. The monitor wafer measuring method comprises the following steps: fixing a product wafer, the product wafer having several alignment marks and product measuring sites corresponding respectively to the alignment marks; determining the product measuring sites according to the alignment marks; and placing a monitor wafer, a projection of the monitor wafer in a vertical direction being aligned with and coinciding with the product wafer. The present application can reduce or even eliminate positional errors of the monitor wafer during a measurement process, such that product-level measuring position accuracy can be achieved for the monitor wafer and further, the measuring machine itself and process changes can be monitored in a better way.

Abstract: Provided is a method for generating a chip probing wafer map, and the method includes: obtaining test data associated with a first chip, wherein the first chip includes a plurality of sequentially arranged first dies, and each of the first dies belongs to one of a plurality of bin numbers; assigning different predetermined color codes to the bin numbers; and generating a first general chip probing wafer map for the first chip by assigning a color code of each of the first dies as a corresponding predetermined color code according to the bin number to which each of the first dies belongs.

Abstract: A device for determining an effective piezoelectric coefficient of a thin film of a material of a sample, includes a source of x-rays incident on the sample; a detector of x-rays diffracted by the sample; a device for positioning the x-ray source and the x-ray detector with respect to the sample; a voltage source making contact with the sample; a device for controlling the voltage source so as to apply an electric field to the sample during an electrical cycle, the electric field generating a strain of the sample and a stress on the sample; a device for measuring a diffraction peak of the x-rays as a function of the electric field applied to the sample during the electrical cycle; a processing device configured to determine the piezoelectric coefficient.

Abstract: The present disclosure provides an electrical test structure, a semiconductor structure and an electrical test method. In the electrical test structure, in a first direction, the electrical test structure includes a first layer, an interconnect hole and a second layer arranged in a stack, and the interconnect hole is in contact with the first layer; the second layer includes a body part and a test part, and the test part is connected to the body part; the interconnect hole is configured as, when an offset distance of the interconnect hole relative to a preset position in a second direction is less than a first preset distance, or an offset distance of the interconnect hole relative to the preset position in a third direction is less than a second preset distance, the interconnect hole is spaced apart from the test part.

Abstract: According to some aspects, a portable magnetic resonance imaging system is provided, comprising a B0 magnet configured to produce a B0 magnetic field for an imaging region of the magnetic resonance imaging system, a noise reduction system configured to detect and suppress at least some electromagnetic noise in an operating environment of the portable magnetic resonance imaging system, and electromagnetic shielding provided to attenuate at least some of the electromagnetic noise in the operating environment of the portable magnetic resonance imaging system, the electromagnetic shielding arranged to shield a fraction of the imaging region of the portable magnetic resonance imaging system. According to some aspects, the electromagnetic shield comprises at least one electromagnetic shield structure adjustably coupled to the housing to provide electromagnetic shielding for the imaging region in an amount that can be varied.

Abstract: A substrate is provided. The substrate includes a front region having a front surface, a back region having a back surface, an edge exclusion region, and a chamfered surface. The back surface is laterally opposite the front surface. The edge exclusion region is surrounding the front region. The chamfered surface is at least partially arranged in the edge exclusion region.

Abstract: Embodiments of the present invention provide testing systems with liquid cooled thermal arrays that can pivot freely in three dimensions allowing surfaces to be brought into even, level, and secure contact, thereby preventing air gaps between surfaces and improving thermal performance. In this way, more DUTs can be tested in parallel within a small test space, overall costs of the test system are reduced, and greater cooling capacity can be provided for testing high-powered devices. Gimbaled mounts are disposed on a bottom surface of individual thermal interface boards (TIBs) of a test system, and/or on top of individual thermal heads of a thermal array (TA) having a common cold plate (or having multiple cold plates).

Abstract: An object is to provide a technique capable of creating a precise measurement condition in a facilitated manner relating to an electrical characteristic inspection for a semiconductor device. An electrical characteristic inspection device includes a storage unit configured to store a measurement condition of the semiconductor device being an inspection subject, a control unit configured to read out the measurement condition corresponding to inspection contents to be executed from the storage unit, an inductive inductance control circuit unit configured to set inductive inductance for the semiconductor device, and a floating inductance control circuit unit configured to set floating inductance for the semiconductor device. Based on the measurement condition read out from the storage unit, the control unit is configured to adjust the inductive inductance by controlling the inductive inductance control circuit unit, and adjust the floating inductance by controlling the floating inductance control circuit unit.

Abstract: The present disclosure provides a system for perceiving an operating state of a large power transformer based on vibro-acoustic integration, including a perception layer, a network layer, and a diagnostic layer, where the perception layer is used for monitoring, in real time, a state parameter for a coupling vibration signal and an acoustic signal of each of a transformer core, a winding, a clamp and a housing, a state parameter of each of a vibration signal and an acoustic signal during a gear position change of an on-load tap changer (OLTC), and preliminarily diagnosing and analyzing monitored data. The system can monitor the operating state of the OLTC online for a long time, flexibly configure the sensor channel and the sensor type according to different application requirements, automatically acquire and identify the gear position change, and correctly identify and process a gear position corresponding to the monitoring signal.

Abstract: A method of determining polymerisation of transformer insulation within a transformer. The method includes the steps of measuring a first and second moisture activity of oil in a transformer, and a first and second temperature of the transformer. The method further includes calculating the ratio of the gradients of the moisture equilibrium curves associated with the moisture activity and the temperature. The calculated ratio can then be used to characterise the polymerisation of the insulation and age of the transformer.

Abstract: A method for testing at least one single chip in a wafer probing system, at least comprising: providing an adapter plate having an interface surface for contacting a vacuum chuck of the wafer probing system, the adapter plate being configured to accommodate the at least one single chip in a cutout with a chip rear surface being flush with the interface surface; loading the adapter plate with the at least one single chip into the wafer probing system; determining an exact position of the at least one single chip in the adapter plate in the search area; and testing the at least one single chip with test routines stored in a controller of the wafer probing system. A device and an adapter plate for testing at least one single chip in a wafer probing system.

Abstract: A circuit and method for detecting crack damage of a die are provided. The circuit comprises: a test circuit located within a seal ring of the die for outputting a pulse detection signal; a crack detection loop arranged outside a guard ring of an internal processing circuit of the die, having an input end connected to an output end of the test circuit and an output end connected to an output pin of the die; and a relay driving unit arranged between the input end and output end for increasing a capability of transmission of the pulse detection signal, wherein the seal ring surrounds the whole die; in a test mode, the test circuit outputs the pulse detection signal to the crack detection loop, and a test machine determines whether the die is damaged by a crack by reading a signal on the output pin of the die.

Abstract: A flow cell assembly for use in NMR measurements on a liquid NMR sample in an NMR spectrometer has a cylindrical flow cell for receiving the NMR sample, with a first opening at a first end and a second opening at a second end, and a connecting piece arranged at the first opening for connecting a flow line to the flow cell in a fluid-tight manner. An opening diameter dop of the first opening is smaller than an inner flow cell diameter din, and a sealing head of the connecting piece is arranged in the first opening, with a sealing head diameter dseal larger than dop. For NMR measurements, the flow cell assembly is modified in such a way that the flow lines can be easily exchanged, and high-quality NMR flow measurements can be carried out independently of the orientation of the magnetic field in the NMR spectrometer.

Abstract: Systems, apparatuses, and methods are described for a transformer supporting two or more sets of windings electrically connected to different voltage levels. Use of stress control materials or composite materials (comprising a matrix and filler) may direct electrical fields caused by the different voltage levels to have a lowered electrical field amplitude.

Abstract: A method for medical imaging may include determining a posture of an object and obtaining a first parameter of a pulse sequence to be applied to the object. The method may also include determining, based on the posture and the first parameter, a SAR distribution model and estimating, based on the SAR distribution model and a second parameter of the pulse sequence to be applied, a SAR distribution associated with the object under the pulse sequence to be applied. The second parameter is associated with calibration of the pulse sequence to be applied. The method may further include determining whether the estimated SAR distribution meets a condition and causing, in response to a result of the determination that the estimated SAR distribution associated with the object meets the condition, a scanner to perform an MR scan on the object according to the pulse sequence.

Abstract: Embodiments of the invention include a computer-implemented method that includes controlling, using a processor, a high-resolution optical inspection tool (HROIT) to identify a reference die tamper circuit on a reference die of a wafer; and controlling, using the processor, a low-resolution optical inspection tool (LROIT) to use the reference die tamper circuit to determine that the reference die tamper circuit is on a second die of the wafer.

Abstract: A chip crack detection structure, including a substrate, a first chip crack detection ring, a second chip crack detection ring, and a seal ring, is provided. The first chip crack detection ring includes multiple first conductive layers stacked over the substrate and electrically connected to each other. A bottom surface of a lowermost conductive layer among the first conductive layers is not in contact with any plug. The second chip crack detection ring surrounds the first chip crack detection ring. The second chip crack detection ring includes multiple second conductive layers stacked over the substrate and electrically connected to each other. A bottom surface of a lowermost conductive layer among the second conductive layers is not in contact with any plug. The seal ring surrounds the second chip crack detection ring. The seal ring includes multiple third conductive layers stacked over the substrate and electrically connected to each other.

Abstract: There is provided a control method of a test device, the test device comprising a chuck on which an object to be tested is mounted, a tester configured to supply electric power to the object to be tested to test the object to be tested, and a controller configured to control a temperature of the chuck. The control method comprises: when an actual temperature of the object to be tested cannot be fed back, estimating a temperature difference between the temperature of the chuck and the temperature of the object to be tested on the basis of a heat amount of the object to be tested; correcting a target temperature of the chuck on the basis of a target temperature of the object to be tested and the temperature difference; and controlling the temperature of the chuck on the basis of the corrected target temperature of the chuck and an actual temperature of the chuck.

Abstract: A system for testing a transformer includes a voltage source configured to apply an input voltage to a secondary winding of the transformer, the input voltage is configured to induce a voltage in a primary winding of the transformer. A primary voltmeter is configured to measure the induced voltage in the primary winding, a plurality of secondary voltmeters configured to measure voltage in a plurality of secondary windings of the transformer, and one or more phase angle meters to simultaneously measure a plurality of phase angles between the primary voltage and each of the plurality of secondary voltages. A controller is connected to the voltage source, the primary voltmeter, the plurality of secondary voltmeters, and the one or more phase angle meters, the controller is configured to calculate a plurality of winding ratios based on the voltage and phase angle measurements, the controller is also configured to identify all secondary taps.

Abstract: An inspection terminal provided in a test device has a main body portion including a support portion that is curved; a plate-shaped portion integrally connected to the support portion and extending in a first direction; a tip portion integrally connected to the plate-shaped portion and having a larger dimension in a second direction intersecting with the first direction than that of the plate-shaped portion in the second direction; and a slit formed from the tip portion to the plate-shaped portion so as not to reach the support portion of the inspection terminal. The tip portion of the inspection terminal has a first contact portion and a second contact portion that are separated from each other by way of via the slit, and each contact portion is brought into contact with an external terminal of a semiconductor package, and an electrical test of the semiconductor package is performed.