Patents Examined by Courtney G McDonnough
-
Patent number: 11733298Abstract: The present application provides two-port on-wafer calibration piece circuit models and a method for determining parameters. The method includes: measuring a single-port on-wafer calibration piece circuit model corresponding to a first frequency band to obtain a first S parameter; calculating, according to the first S parameter, an intrinsic capacitance value of a two-port on-wafer calibration piece circuit model corresponding to the single-port on-wafer calibration piece circuit model; measuring the two-port on-wafer calibration piece circuit model corresponding to the terahertz frequency band to obtain a second S parameter; and calculating a parasitic capacitance value and a parasitic resistance value of the two-port on-wafer calibration piece circuit model according to the second S parameter and the intrinsic capacitance value.Type: GrantFiled: December 14, 2021Date of Patent: August 22, 2023Assignee: The 13th Research Institute of China Electronics Technology Group CorporationInventors: Yibang Wang, Aihua Wu, Faguo Liang, Chen Liu, Ye Huo, Peng Luan, Jing Sun, Yanli Li
-
Patent number: 11726075Abstract: Soil moisture monitoring systems and methods for measuring mutual inductance of area of influence using radio frequency stimulus are disclosed herein. An example device includes a master element stacked vertically on top of one or more slave elements. The master element and slave elements can communicate through a 1-wire bus configuration. The master element can determine the presence and location of each of the one or more slave elements using an auto-discovery process. The master element can issue commands to the one or more slave elements to obtain moisture readings and/or temperature readings.Type: GrantFiled: November 29, 2022Date of Patent: August 15, 2023Assignee: FarmX Inc.Inventor: William Eugene Jennings
-
Patent number: 11726136Abstract: A reflectometer for allowing a test of a device, the reflectometer comprising: a source of pulsed radiation; a first photoconductive element configured to output a pulse in response to irradiation from the pulsed source; a second photoconductive element configured to receive a pulse; and a transmission line arrangement configured to direct the pulse from the first photoconductive element to the device under test and to direct the pulse reflected from the device under test to the second photoconductive element. At least one of the first and second photoconductive elements is provided on a different substrate to that of the transmission line arrangement.Type: GrantFiled: October 6, 2021Date of Patent: August 15, 2023Assignee: TeraView LimitedInventor: Bryan Edward Cole
-
Patent number: 11723683Abstract: Systems (10) and methods (12) of controlling an ultrasonic surgical tool (20) with a console (22) are provided. A first drive signal (40) is applied to the ultrasonic surgical tool (20). A characteristic of a harmonic signal (44) resulting from application of the first drive signal (40) to the ultrasonic surgical tool (20) is acquired. A cancellation signal (70) is generated based on the characteristic of the harmonic signal (44). The first drive signal (40) and the cancellation signal (70) are combined to produce a second drive signal (80) that is sinusoidal. The second drive signal (80) is applied to the ultrasonic surgical tool (20) such that presence of the harmonic signal (44) resulting from application of the second drive signal (80) is reduced relative to presence of the harmonic signal (44) resulting from application of the first drive signal (40).Type: GrantFiled: May 23, 2022Date of Patent: August 15, 2023Assignee: Stryker CorporationInventor: Adam Darwin Downey
-
Patent number: 11719744Abstract: An inspection apparatus includes: an acquisition part configured to acquire first coordinate information indicating a position of an inspection object on a stage and a plurality of pieces of second coordinate information indicating positions of a plurality of temperature sensors on the stage when performing an inspection of the inspection object; a calculation part configured to calculate a Mahalanobis distance between a position specified by an average vector of the first coordinate information and the positions of the plurality of temperature sensors; a selection part configured to select at least one temperature sensor including a temperature sensor having a smallest Mahalanobis distance, among the plurality of temperature sensors; and a controller configured to control a temperature of the inspection object using temperature data measured by the selected at least one temperature sensor.Type: GrantFiled: January 12, 2022Date of Patent: August 8, 2023Assignee: Tokyo Electron LimitedInventor: Hiroyuki Nakayama
-
Systems, methods, and apparatus for detecting ferromagnetic foreign objects in a predetermined space
Patent number: 11719847Abstract: An apparatus for detecting a presence of an object includes an inductive sensing coil that is configurable to generate a magnetic field. The inductive sensing coil is configured to have an electrical characteristic that is detectable when generating the magnetic field. The apparatus comprises a controller configured to detect a change in the electrical characteristic and determine a presence of the object based on the detected change in the electrical characteristic.Type: GrantFiled: June 9, 2022Date of Patent: August 8, 2023Assignee: WiTricity CorporationInventors: Hans Peter Widmer, Lukas Sieber, Andreas Daetwyler -
Patent number: 11714122Abstract: A semiconductor device and a method of testing the same are provided. A semiconductor device includes a Design Under Test (DUT), a processing core configured to execute test software to determine an optimum operating voltage of the DUT, and a protection circuit configured to block the transmission of undefined signals generated by the DUT while the processing core executes the test software.Type: GrantFiled: June 4, 2021Date of Patent: August 1, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Joon Woo Cho, Yun Ju Kwon, Sang Woo Kim
-
Patent number: 11714124Abstract: An electronic component handling apparatus handles a device under test (DUT). The electronic component handling apparatus includes: transfer units that each include a DUT transfer part that mounts the DUT on a first tray and removes the DUT from the first tray; contact units that each press the DUT mounted on the first tray against a socket disposed on a test head connected to a tester; and a tray transporter that transports the first tray between the contact units and the transfer units. Either or both of (i) at least one of the contact units and (ii) at least one of the transfer units are removably disposed on the electronic component handling apparatus.Type: GrantFiled: June 25, 2021Date of Patent: August 1, 2023Assignee: ADVANTEST CorporationInventors: Hiromitsu Horino, Yoshitaka Takeuchi, Yoshinori Arai, Hiroyuki Kikuchi
-
Patent number: 11703541Abstract: A semiconductor inspecting method for ensuring a scrubbing length on a pad includes following steps. First off, a first position of a probe needle from above is defined. In addition, a wafer comprising at least a pad is placed on a wafer chuck of a semiconductor inspecting system. Thereafter, a relative vertical movement between the probe needle and the pad is made by adopting a driving system of the semiconductor inspecting system to generate a scrubbing length on the pad. Next, whether the scrubbing length is equal to or larger than a preset value or not is recognized by adopting the vision system and the relative vertical movement is stopped by adopting the driving system.Type: GrantFiled: November 12, 2021Date of Patent: July 18, 2023Inventors: Volker Hansel, Sebastian Giessmann, Frank Fehrmann, Chien-Hung Chen
-
Patent number: 11693043Abstract: A test head assembly for a semiconductor device has a carrier, a pin seat and a test wire assembly. The carrier is formed in an L shape and has a lateral board, a perpendicular board and a opening formed through the perpendicular board. The pin seat is mounted in the corresponding opening. The test wire assembly has a test head, a plurality of connectors and a plurality of test wires. The test head is mounted on an outer sidewall of the lateral board and connected to the pin seat through the test wires and the connectors. Therefore, the pin seat is mounted on the perpendicular board of the L-shaped uprightly and the test head is mounted on the lateral board. The pin seat and the test head are not parallel to each other, and a lateral size of the test head assembly is reduced to increase the space usage.Type: GrantFiled: September 3, 2021Date of Patent: July 4, 2023Assignee: Powertech Technology Inc.Inventors: Ying-Tang Chao, Yen-Yu Chen, Shin-Kung Chen
-
Patent number: 11693039Abstract: A device provides high impedance contact pads for an electrostatic charge sensor. The contact pads are shared between the electrostatic charge sensor and drivers. The contact pads are set to a high impedance state by reducing current leakage through the drivers. Compared to electrostatic charge sensor with low impedance contact pads, the electrostatic charge sensor disclosed herein has high sensitivity, and is able to detect weak electrostatic fields.Type: GrantFiled: November 29, 2021Date of Patent: July 4, 2023Assignee: STMICROELECTRONICS S.R.L.Inventor: Massimo Orio
-
Patent number: 11680974Abstract: A method for monitoring polarization quality of a piezoelectric film is described. In this method, a detection step is performed on a piezoelectric film by using a detection device with a non-contact method during a polarization process of the piezoelectric film, to obtain a static electricity information or a transmittance information. A determination step is performed by using the static electricity information or the transmittance information to determine a polarization degree of the piezoelectric film.Type: GrantFiled: May 25, 2021Date of Patent: June 20, 2023Assignee: CREATING NANO TECHNOLOGIES. INC.Inventors: Ji-Yung Lee, Andrew Ronaldi Tandio, Hung-Chan Chiang, Bo-Fan Tsai
-
Patent number: 11668747Abstract: A control method of an inspection apparatus including a mounting stage on which a substrate having a plurality of inspection objects is mounted, a plurality of sections being formed with respect to the mounting stage and a heater controllable to heat for each of the sections includes when inspecting a first inspection object to be inspected among the plurality of inspection objects, causing the heater to heat a section corresponding to the first inspection object and a section corresponding to a second inspection object to be inspected next.Type: GrantFiled: July 26, 2021Date of Patent: June 6, 2023Assignee: Tokyo Electron LimitedInventors: Naoki Akiyama, Hiroyuki Nakayama
-
Patent number: 11662326Abstract: The present invention provides a method for calculating the liquid-solid interface morphology during growth of the ingot. The method comprises providing a wafer, selecting plural sampling locations on the wafer and detecting electrical resistivity at the plural sampling locations, calculating height differences between the sampling locations based on the detected electrical resistivity, and illustrating the morphology of the liquid-solid interface based on the calculated height differences. The method of the invention has advantages including easy operation and low cost.Type: GrantFiled: February 4, 2021Date of Patent: May 30, 2023Assignee: Zing Semiconductor CorporationInventors: Yan Zhao, Nan Zhang, Qiang Chen, Hanyi Huang
-
Patent number: 11656274Abstract: A system and method for evaluating the reliability of semiconductor die packages are configured to sort a plurality of semiconductor dies with a Known Good Die (KGD) subsystem based on a comparison of an inline part average testing (I-PAT) score of each of the plurality of semiconductor dies to a plurality of I-PAT score thresholds, where the semiconductor die data includes the I-PAT score for each of the plurality of semiconductor dies, where the I-PAT score represents a weighted defectivity of the corresponding semiconductor die. The semiconductor dies may be filtered to remove at-risk semiconductor dies prior to sorting. The semiconductor die data may be received from a plurality of semiconductor die supplier subsystems. The KGD subsystem may transmit semiconductor die reliability data about the sorted plurality of semiconductor dies to a plurality of semiconductor die packager subsystems.Type: GrantFiled: March 25, 2021Date of Patent: May 23, 2023Assignee: KLA CorporationInventors: Robert J. Rathert, David W. Price, Chet V. Lenox, Oreste Donzella
-
Patent number: 11644500Abstract: In one example, a first tubular member has a first diameter and is configured to attach to a printed circuit board. A second tubular member has a second diameter different from the first diameter and is configured to hold an environmental sensor for collecting data relating to an environment of the printed circuit board. The second tubular member is vertically adjustable relative to the first tubular member.Type: GrantFiled: September 21, 2021Date of Patent: May 9, 2023Assignee: CISCO TECHNOLOGY, INC.Inventors: Mohammed Ghouse, Shailesh Nayak, Damaruganath Pinjala, Rohit Dev Gupta, Mehmet Onder Cap
-
Patent number: 11639959Abstract: A system and method for defect localization in embedded memory are provided. Embodiments include a system including automated testing equipment (ATE) interfaced with a wafer probe including a diagnostic laser for stimulating a DUT with the diagnostic laser at a ROI. The ATE is configured to simultaneously perform a test run at a test location of the DUT with a test pattern during stimulation of the DUT. Failing compare vectors of a reference failure log of a defective device are stored. A first profile module is configured to generate a first 3D profile from each pixel of a reference image of the defective device. A second profile module is configured to generate a second 3D profile from each pixel of the ROI of the DUT. A cross-correlation module is configured to execute a pixel-by-pixel cross-correlation from the first and second 3D profiles and generate an intensity map corresponding to a level of correlation between the DUT and defective device.Type: GrantFiled: February 18, 2021Date of Patent: May 2, 2023Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Szu Huat (Wu Shifa) Goh, Yin Hong Chan, Boon Lian Yeoh, Lin Zhao, Man Hon Thor
-
Patent number: 11635461Abstract: A test apparatus and method for testing a semiconductor device. The semiconductor device includes an integrated circuit and a plurality of external radiating elements located at a surface of the device. The external radiating elements include at least one transmit element and receive element. The test apparatus includes a plunger. The plunger includes a dielectric portion having a surface for placing against the surface of the device. The plunger also includes at least one waveguide. Each waveguide extends through the plunger for routing electromagnetic radiation transmitted by one of the transmit elements of the device to one of the receive elements of the device. Each waveguide comprises a plurality of waveguide openings for coupling electromagnetically to corresponding radiating elements of the device. The dielectric portion is configured to provide a matched interface for the electromagnetic coupling of the waveguide openings to the plurality of external radiating elements of the device.Type: GrantFiled: December 8, 2020Date of Patent: April 25, 2023Assignee: NXP B.V.Inventors: Abdellatif Zanati, Henrik Asendorf, Jan-Peter Schat, Nicolas Lamielle
-
Patent number: 11630147Abstract: The present invention relates to a low-thermal resistance pressing device for a socket, which mainly comprises a housing, an inner collar, a heat conductive pressing block, a bearing collar and a locking member. The locking member on the housing is used to lock the socket. The inner collar is threadedly engaged with the housing. The bearing collar is located between the inner collar and the heat conductive pressing block. In the case of rotating the inner collar in the housing, the bearing collar drives the heat conductive pressing block to move axially so as to exert an axial force to a device to be tested. Because the heat conductive pressing block protrudes from the upper and lower surfaces of the housing, one end thereof can be in contact with a temperature control module, and the other end thereof can be in contact with the device to be tested.Type: GrantFiled: December 15, 2021Date of Patent: April 18, 2023Assignee: CHROMA ATE INC.Inventors: Ming Cheng Huang, Tsung-I Lin, Hui-Jung Wu, Chien-Ming Chen
-
Patent number: 11624767Abstract: A semiconductor test apparatus according to the present disclosure includes: a stage on which a wafer is to be mounted; a pressurizing wall disposed on a surface of a probe card opposing the stage, extending toward the stage, and having an opening; a mark disposed on a lower surface of the pressurizing wall opposing the stage; a probe disposed in the opening; an air tube to force air into the opening; a detector to detect first spacing between a tip of the probe and the mark; and a controller to control second spacing between the wafer and the lower surface of the pressurizing wall based on the first spacing, wherein, when an electrical property of each of chips of the wafer is measured, the second spacing is controlled to be predetermined spacing by the controller, and the air is forced into the opening through the air tube.Type: GrantFiled: July 27, 2021Date of Patent: April 11, 2023Assignee: Mitsubishi Electric CorporationInventors: Yasushi Takaki, Kinya Yamashita, Masaki Ueno