Abstract: A fault detection circuit includes a short circuit comparison circuit which has a first input connected to the source of the second NFET, a second input, and an output. The circuit includes an over-current comparison circuit which has a first input connected to the source of the second NFET, a second input, and an output. The circuit includes a voltage divider circuit which has a first terminal connected to first input of the short circuit comparison circuit, a second terminal connected to the first input of the over-current comparison circuit, and a third terminal connected to a ground terminal. The circuit includes a delay circuit which has an input connected to the output of the over-current comparison circuit and has an output.

Abstract: A wafer inspection system and a wafer inspection equipment thereof are provided. The wafer inspection system includes a susceptor device, probe card, and bridge module. The susceptor device includes a susceptor unit for placing a wafer under test. The probe card includes a probing portion and conducting portion. The conducting portion is disposed at the periphery of the probing portion and has a contact surface. The bridge module includes transmission units extended upward, positioned adjacent to a wafer placement area, and coupled to the susceptor unit. When the probing portion comes into contact with a testing point of the wafer, the contact surface of the conducting portion gets coupled to the transmission units to transmit a test signal to the probe card via the transmission units and conducting portion and thus form a test loop. Thus, the test loop path can be shortened and the accuracy of signal transmission and inspection can be enhanced.

Abstract: A system to detect gate-open failures in a MOS based insulated gate transistor can include a detection circuit, including a first circuit configured to measure a drain-source voltage across the MOS based insulated gate transistor, a first comparator circuit can be configured to compare the measured drain-source voltage to a threshold drain-source conduction voltage indicating a conduction state of a channel of the MOS based insulated gate transistor, a second circuit can be configured to measure a gate voltage applied at a gate of the MOS-based insulated gate transistor, a second comparator circuit can be configured to compare the gate voltage applied at the gate to a threshold gate voltage for the MOS based insulated gate transistor to provide an indication of whether the gate voltage applied at the gate is sufficient to activate conduction in the channel and a logic circuit can be configured to detect a gate-open failure of the MOS based insulated gate transistor based on the conduction state of the channel

Abstract: An electronic component handling apparatus handles a device under test (DUT). The electronic component handling apparatus includes: contact units that adjust a temperature of the DUT independently from one another and press the DUT against a socket independently from one another. The socket is disposed on a test head that is mounted to each of the contact units and that is connected to a tester. At least one of the contact units is removably disposed on the electronic component handling apparatus.

Abstract: An inspection apparatus includes a light sensor that detects light from a semiconductor device to which an electric signal has been input, an optical system that guides light from the semiconductor device to the light sensor, and a control device electrically connected to the light sensor. The control device includes a measurement unit that acquires waveform data obtained by optical measurement for each of a plurality of positions on a defective semiconductor device and waveform data obtained by the optical measurement for each of a plurality of positions on a non-defective semiconductor device, a calculation unit that calculates a degree of correspondence between the waveform data of the defective semiconductor device and the waveform data of the non-defective semiconductor device, and an analysis unit that analyzes a defective part of the defective semiconductor device on the basis of the degree of correspondence for each of the plurality of positions.

Abstract: A remote control device testing environment evaluates operational performance of physical implementations of remote control devices. This operational performance of the physical implementations of the remote control devices allows the integrated circuits of the remote control devices as well as integrated circuit interfaces electrically coupling these integrated circuits to each other to be evaluated. Additionally, the interconnection, such as electrical coupling to provide an example, between these integrated circuits and/or the integrated circuit interfaces can be evaluated which otherwise would not be evaluated by software simulation alone. Moreover, the evaluating of this operational performance of the physical implementations of the remote control devices allows these remote control devices to be in evaluated in a real world environment with exposure to various environmental factors, such as temperature, humidity, and/or electromagnetic interference to provide some examples.

Abstract: An inspection device includes a reference signal output section, a noise removal section, and an electrical characteristic measurement section. The reference signal output section is connected to an external power supply device in electrical parallel with a semiconductor sample, and outputs a reference signal according to the output of the external power supply device. The noise removal section outputs a noise removal signal obtained by removing a noise component of the output of the external power supply device from the current signal output from the semiconductor sample based on the reference signal. The electrical characteristic measurement section measures the electrical characteristic of the semiconductor sample based on the noise removal signal. The inspection device measures the electrical characteristic of the semiconductor sample to which a voltage is being applied by the external power supply device and which is being irradiated and scanned with light.

Abstract: Methods of characterizing electrical properties of a semiconductor layer structure on a wafer with topside semiconductor layers on an insulating or semi-insulating substrate, the semiconductor layer structure including a high electron mobility transistor (HEMT) heterostructure with a two-dimensional electron gas (2DEG) at a heterointerface between the semiconductor layers of the heterostructure. The methods include: (a) physically contacting the topside of the wafer within a narrow border zone at an edge of the wafer with a flexible metal cantilever electrode of a contacting device, wherein the flexible metal cantilever electrode contacts one or more of the semiconductor layers exposed at the narrow border zone so that the flexible metal cantilever electrode is in electrical contact with the 2DEG; and (b) applying corona charge bias and measuring a surface voltage of the semiconductor layers using a non-contact probe while maintaining the electrical contact with the 2DEG.

Abstract: A method includes capturing a photon emission microscope (PEM) image of an integrated circuit (IC), and identifying emission sites in the PEM image, where the emission sites are associated with a leakage current. A set of common nets is found that connects multiple emission sites using layout data and/or netlist data in computer-aided design (CAD) data. From the layout data and/or netlist data, a critical net is identified from the set of common nets connecting a threshold number of emission sites. The critical net is cross-mapped, by a processor, tip netlist data in the CAD data. A particular device is identified from the netlist data that has an output pin connected to the critical net. The particular device identified from the netlist data is cross-mapped, by a processor, to the layout data, wherein the critical net connects at least two devices at the identified emission sites including the particular device.

Abstract: A test device includes: a plurality of signal test pads electrically connected to pads of an input sensing unit; a power test pad electrically connected to a power pattern of a display unit; a test circuit configured to apply a test signal to the signal test pads; a voltage generator configured to generate a sensing power voltage; and a ripple controller configured to change a voltage level of the sensing power voltage to apply the sensing power voltage to the power test pad.

Abstract: An inspection apparatus includes a stage on which a substrate is placed, a cooler, a probe card, a light irradiator and a controller. The cooler cools the substrate placed on the stage. The probe card has probes to be in contact with the substrate to supply electric power. The light irradiator irradiates light to an upper surface of the substrate, opposite to a bottom surface of the substrate placed on the stage. Further, the controller controls the light irradiator.

Abstract: There is provided a system and a method of testing an optical device in a scanner for scanning a semiconductor specimen, the method comprising controlling, by a processor and memory circuitry (PMC) operatively connected to the scanner, an optical element optically connected to the optical device to deviate an optical path of light transmitted by the optical device so to transmit towards an imaging sensor, thereby enabling acquiring, by the imaging sensor, image data informative of the optical device, wherein in a scanning mode the optical element enables light transmitting from the optical device towards another optical device comprised in the scanner, and processing the acquired image data to obtain results informative of operability of the optical device.

Abstract: An inspection apparatus for inspecting a backside irradiation type imaging device formed on an inspection object includes: a stage on which the inspection object is mounted such that the stage faces a rear surface of the backside irradiation type imaging device, wherein the stage includes: a transmitter including a flat plate formed of a light transmitting material, and configured to mount the inspection object on the transmitter; and a light emitter disposed at a location facing the inspection object with the transmitter interposed between the light emitter and the inspection object, and configured to emit light toward the transmitter, and wherein the transmitter transmits the light from the light emitter while diffusing the light.

Abstract: A semiconductor module inspection device is provided. The semiconductor module inspection device includes a receiver to store semiconductor modules; a loader to receive a semiconductor module from the receiver; a testing unit to receive the semiconductor module from the loader and perform a test process on the semiconductor module; an unloader to receive the semiconductor module from the testing unit and provide the semiconductor module from the testing unit to the receiver; and robots for transporting the semiconductor module. The robots include: a first robot to transport the semiconductor module from the receiver to the loader, a second robot to transport the semiconductor module from the loader to the testing unit, a third robot to transport the semiconductor module from the testing unit to the unloader, and a fourth robot to transport the semiconductor module from the unloader to the receiver.

Abstract: Soil moisture monitoring systems and methods for measuring mutual inductance of area of influence using radio frequency stimulus are disclosed herein. An example device includes a master element stacked vertically on top of one or more slave elements. The master element and slave elements can communicate through a 1-wire bus configuration. The master element can determine the presence and location of each of the one or more slave elements using an auto-discovery process. The master element can issue commands to the one or more slave elements to obtain moisture readings and/or temperature readings.

Abstract: One embodiment of the present invention provides a method for evaluating the electrical defect density of a semiconductor layer, which comprises: a step for measuring an electric current by applying a voltage to a semiconductor element 1 which comprises a GaN layer 12 that serves as a semiconductor layer; and a step for deriving the electrical defect density in the GaN layer 12 with use of the measured electric current value.

Abstract: A test handler includes a pusher which includes a pusher end which comes into contact with a DUT (Device Under Test) to transfer heat, and a pusher body which conducts heat to the pusher end, the pusher end separating a test tray for fixing the DUT and the pusher body from each other; a porous match plate including a pusher arrangement region in which the pusher body is placed, and a plurality of holes placed adjacent to the pusher arrangement region; a heater placed on an upper surface of the porous match plate to control temperature of the pusher; and an airflow input port placed on the heater to provide the airflow to the plurality of holes, in which the airflow passes through the plurality of holes and passes through a separated space between the test tray and the pusher body.

Abstract: A balanced on-wafer load pull tuner system includes an intelligent, independent and universal mechanical balancing and contact controlling device, supporting automatic microwave single or multi-probe slide screw tuners. It allows contacting and stable on-wafer testing of sub-micrometric devices. Ultra-low loss rigid airlines (bend-lines) used to connect the tuner with the semiconductor chips, in order to improve the tuning range at the DUT reference plane, transfer mechanical movements of the wafer probes attached to the rigid bend-lines, when the tuner mobile carriages move horizontally. A precisely controlled counter-weight allows contacting the DUT and balanced load pull operation by controlling the center of gravity of the assembly.

Abstract: A semiconductor component burn-in test module includes a burn-in board and an external power transmission component. The burn-in board includes a plurality of burn-in seats, wherein a plurality of chips are disposed on the burn-in seats. The external power transmission component is arranged at opposite two sides of the burn-in board, where the external power transmission component includes a plurality of conductive members and a plurality of terminal seats. The burn-in board is provided with a plurality of wirings corresponding to the external power transmission component. As such, electric power can be conveyed to the plural burn-in seats of the burn-in board, through the plural terminal seats and the plural conductive strips. This decreases the length and the number of copper foil wirings in the burn-in boards for power transmission, so as to lower the cost of the burn-in boards.

Abstract: A method of determining polymerisation of transformer insulation within a transformer. The method includes the steps of measuring a first and second moisture activity of oil in a transformer, and a first and second temperature of the transformer. The method further includes calculating the ratio of the gradients of the moisture equilibrium curves associated with the moisture activity and the temperature. The calculated ratio can then be used to characterise the polymerisation of the insulation and age of the transformer.