Patents Examined by Craig Goldschmidt
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Patent number: 9983893Abstract: When a guest of a virtual machine attempts to accesses an address that causes an exit from the guest to the hypervisor of a host, the hypervisor receives an indication of an exit by a guest to the hypervisor. The received address is associated with a memory-mapped input-output (MMIO) instruction. The hypervisor determines, based on the received indication, that the exit is associated with the memory-mapped input-output (MMIO) instruction. The hypervisor identifies the address that caused the exit as a fast access address. The hypervisor identifies one or more memory locations associated with the fast access address, where the one or more memory locations store information associated with the MMIO instruction. The hypervisor identifies the MMIO instruction based on the stored information. The hypervisor executes the MMIO instruction on behalf of the guest.Type: GrantFiled: October 1, 2013Date of Patent: May 29, 2018Assignee: Red Hat Israel, Ltd.Inventors: Michael Tsirkin, Gleb Natapov
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Patent number: 9933950Abstract: Apparatuses, systems, methods, and computer program products are disclosed for interrupting storage operations. A frequency module is configured to determine a frequency for pausing a storage operation. An interrupt module is configured to pause execution of a storage operation according to a determined frequency. A resume module is configured to continue a paused storage operation in response to a trigger.Type: GrantFiled: March 12, 2015Date of Patent: April 3, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Jea Hyun, James Peterson, Long Pham, John Strasser, Hairong Sun, Kapil Verma
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Patent number: 9927989Abstract: A method for storing data includes establishing an extended generation group comprising a plurality of data sets. The plurality of data sets include a first data set containing primary members and a first number of generations of each of the primary members, and a second data set containing a second number of generations of each of the primary members. The first data set and the second data set are stored on different tiers of a tiered storage system, and may even be stored on different volumes. The first data set may be stored on higher performance storage media and the second data set may be stored on lower performance storage media. Additionally, the second number will typically be greater than the first number so that more generations are stored on lower performance storage media. A corresponding system and computer program product are also disclosed.Type: GrantFiled: November 1, 2015Date of Patent: March 27, 2018Assignee: International Business Machines CorporationInventors: Derek L. Erdmann, David C. Reed, Thomas C. Reed, Max D. Smith
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Patent number: 9898210Abstract: A method, and system for implementing enhanced fast full synchronization for remote disk mirroring in a computer system. A source backup copy is made locally available to a target for remote disk mirroring. Sectors are identified that are different between the source and target. A hash function is used over a block to be compared, with an adaptive number of tracking sectors per block, starting with a minimum block size.Type: GrantFiled: July 26, 2016Date of Patent: February 20, 2018Assignee: International Business Machines CorporationInventors: Aaron T. Albertson, Robert Miller, Brian A. Nordland, Kiswanto Thayib
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Patent number: 9858073Abstract: The present application provides a method of randomly accessing a compressed structure in memory without the need for retrieving and decompressing the entire compressed structure.Type: GrantFiled: February 11, 2009Date of Patent: January 2, 2018Assignee: LINEAR ALGEBRA TECHNOLOGIES LIMITEDInventor: David Maloney
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Patent number: 9836108Abstract: In a memory system in an embodiment, in a case of normal operation, a control unit returns a write completion response upon completion of reception of write data from a host, and writes the write data into nonvolatile memory in a multiple values. In a case of unordinary power-off, changeover to operation using a backup battery is conducted and the control unit writes dirty data that is not completed in writing into the nonvolatile memory, into the nonvolatile memory with two values. When next boot, the control unit reads the dirty data from the nonvolatile memory into the volatile memory, and thereafter writes the dirty data into the nonvolatile memory in a multiple values.Type: GrantFiled: March 12, 2015Date of Patent: December 5, 2017Assignee: Toshiba Memory CorporationInventors: Yoshihisa Kojima, Katsuhiko Ueki
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Patent number: 9817577Abstract: A data storage device comprises a non-volatile memory comprising a plurality of blocks, each configured to store a plurality of physical pages at predetermined physical locations. A controller programs and reads data stored in a plurality of logical pages. A volatile memory comprises a logical-to-physical address translation map configured to enabling determination of the physical location, within one or more physical pages, of the data stored in each logical page. A plurality of journals may be stored, each comprising a plurality of entries associating one or more physical pages to each logical page. At startup, the controller may read at least some of the plurality of journals in an order and rebuild the map; indicate a readiness to service data access commands after the map is rebuilt; rebuild a table from the map and, based thereon, select block(s) for garbage collection after having indicated the readiness to process the commands.Type: GrantFiled: September 26, 2016Date of Patent: November 14, 2017Assignees: Western Digital Technologies, Inc., Skyera, LLCInventors: Andrew J. Tomlin, Justin Jones, Rodney N. Mullendore
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Patent number: 9792053Abstract: According to one embodiment, a controller for a nonvolatile semiconductor memory that stores data expressed using n levels (n is a natural number not less than 3) page by page includes an extraction unit and a conversion unit. The extraction unit extracts a second data stream shorter than a first data stream from the first data stream that includes a plurality of data written to the nonvolatile semiconductor memory. The conversion unit converts the second data stream into a third data stream longer than the second data stream, when a difference between threshold voltages of the nonvolatile semiconductor memory corresponding to adjacent two data included in the second data stream is a first level difference. The third data stream has a second level difference smaller than the first level difference.Type: GrantFiled: August 24, 2015Date of Patent: October 17, 2017Assignee: Toshiba Memory CorporationInventor: Shinichi Kanno
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Patent number: 9792181Abstract: Systems, methods, and computer program products for providing operating system (O/S) redundancy in a computing system are provided. One system includes a host computing device, a plurality of memory devices, and a sub-loader coupled between the host computing device and the plurality of memory devices. Each memory device stores a respective O/S and the sub-loader is configured such that the plurality of memory devices appear transparent to the host computing device. One method includes designating, a first logical unit device as a primary logical unit device and subsequently determining that the first logical unit device is unresponsive. The designation is removed from the first logical unit device and a second logical unit device is designated as a new primary logical unit device. One computer program product includes instructions for performing the above method.Type: GrantFiled: February 22, 2010Date of Patent: October 17, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Juan A. Coronado, Lisa R. Martinez, Raul E. Saba
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Patent number: 9785552Abstract: According to one embodiment, a computer system includes a first memory unit, a second memory unit having a data transfer rate lower than that of the first memory unit and a controller. The controller controls transfer of unit data. The unit data includes an indicating portion indicating whether the unit data is to be retained in the second memory unit. When the unit data is transferred from the second memory unit to the first memory unit and the unit data is to be retained in the second memory unit, the controller sets a first state to the indicating portion of the respective unit data. When the unit data is transferred from the first memory unit to the second memory unit, the controller writes the respective unit data in which the indicating portion is set to the first state, to the second memory unit.Type: GrantFiled: May 27, 2015Date of Patent: October 10, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Shinichi Kanno, Hideki Yoshida
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Patent number: 9778885Abstract: In various embodiments, a high-density solid-state storage unit includes a plurality of flash cards. Each flash card has a flash controller that incorporates one or more resources for facilitating compression and decompression operations. In one aspect, data reduction and data reconstruction operations can be performed in-line as data is stored to and retrieved from flash memory. In another aspect, data reduction and data reconstruction operations can be performed as a service. Any one of the plurality of flash cards can be used to provide data reduction or data reconstruction services on demand for any type of data, including system data, libraries, and firmware code.Type: GrantFiled: December 17, 2013Date of Patent: October 3, 2017Assignee: Skyera, LLCInventors: Radoslav Danilak, Rodney N. Mullendore
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Patent number: 9773129Abstract: Embodiments of the present disclosure describe a system and method for providing anti-replay protection. One embodiment describes a system comprising: a security device; and an anti-replay protected flash device comprising: a flash memory array; an authentication unit; and a secure memory, wherein the authentication unit and the secure memory are disposed in a security boundary.Type: GrantFiled: June 28, 2013Date of Patent: September 26, 2017Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.Inventor: Mark Buer
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Patent number: 9760489Abstract: A mechanism is provided for memory coherence in a multiple processor system. Responsive to a memory operation from a processing core of the multiple processor system resulting in a cache miss, the mechanism checks a private region table associated with the processing core. The memory operation attempts to access a memory region. Responsive to determining the memory region corresponds to an entry in the private region table, the mechanism performs a remote memory controller snoop of a remote memory controller without snooping the multiple processor system.Type: GrantFiled: July 15, 2016Date of Patent: September 12, 2017Assignee: International Business Machines CorporationInventors: David M. Daly, Vijayalakshmi Srinivasan
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Patent number: 9760490Abstract: A mechanism is provided for memory coherence in a multiple processor system. Responsive to a memory operation from a processing core of the multiple processor system resulting in a cache miss, the mechanism checks a private region table associated with the processing core. The memory operation attempts to access a memory region. Responsive to determining the memory region corresponds to an entry in the private region table, the mechanism performs a remote memory controller snoop of a remote memory controller without snooping the multiple processor system.Type: GrantFiled: July 15, 2016Date of Patent: September 12, 2017Assignee: International Business Machines CorporationInventors: David M. Daly, Vijayalakshmi Srinivasan
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Patent number: 9747287Abstract: Disclosed is an improved approach for managing updates to metadata for a virtualization environment. According to some embodiments, a compare and swap approach is taken to manage updates and to handle possible inconsistencies.Type: GrantFiled: August 1, 2012Date of Patent: August 29, 2017Assignee: Nutanix, Inc.Inventors: Rishi Bhardwaj, Venkata Ranga Radhanikanth Guturi, Mohit Aron
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Patent number: 9740565Abstract: A request is received to determine a consistent point of data stored in a file system of a storage system having storage units. In response to the request, a prime dependency list is retrieved from a first prime segment stored in a first storage unit, the prime dependency list including information identifying at least a second prime segment stored in a second storage unit. The first and second prime segments are identified by a first prime segment identifier (ID) and a second prime segment ID, respectively, which collectively identify a prime representing a first consistent view of the file system. The consistent point of data is determined based the prime segments listed in the prime dependency list, where the consistent point of data represents a file system state at a point in time for restoration of the file system back to a prior known state.Type: GrantFiled: July 10, 2015Date of Patent: August 22, 2017Assignee: EMC IP Holding Company LLCInventors: Soumyadeb Mitra, Windsor W. Hsu
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Patent number: 9733831Abstract: In a multiprocessor system, a central memory synchronization module coordinates memory synchronization requests responsive to memory access requests in flight, a generation counter, and a reclaim pointer. The central module communicates via point-to-point communication. The module includes a global OR reduce tree for each memory access requesting device, for detecting memory access requests in flight. An interface unit is implemented associated with each processor requesting synchronization. The interface unit includes multiple generation completion detectors. The generation count and reclaim pointer do not pass one another.Type: GrantFiled: July 1, 2014Date of Patent: August 15, 2017Assignee: GLOBALFOUNDRIES INC.Inventor: Martin Ohmacht
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Patent number: 9720618Abstract: A method and system for synthesizing backup snapshots is discussed. IO's may be streamed from multiple locations, and placed in journal files. These journal files may thereafter be used to synthesize the backup snapshot.Type: GrantFiled: December 16, 2013Date of Patent: August 1, 2017Assignee: EMC IP Holding Company LLCInventors: Anestis Panidis, Assaf Natanzon, Saar Cohen
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Patent number: 9703485Abstract: Methods for deciding whether to store data in a non-volatile memory (NVM) storage portion of a hybrid drive including the NVM storage portion and a disk storage portion are provided. One such method involves generating a queue for storing candidate addresses and a priority level for each of the candidate addresses, receiving a read command and a range of addresses for the disk storage portion, determining a relative distance between reads of a first address corresponding with a second address within the range of addresses, storing, when the relative distance is less than a relative distance threshold, a first candidate address, corresponding to the second address, and a respective priority level in the queue, and storing, when the priority level of the first candidate address is greater than a priority level threshold, data corresponding to the first candidate address in the NVM storage portion.Type: GrantFiled: July 15, 2015Date of Patent: July 11, 2017Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: David Robison Hall, Mark Andrew Jerde
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Patent number: 9685220Abstract: There are provided a DDR controller, a method for implementing the same and a chip, which are applicable to the field of DDR controller technology. The method includes the steps of: parsing a plurality of buffered commands concurrently (S501); prejudging relationships between a bank and a row of an address to be accessed by each parsed command and a bank and a row of an address for a currently executed command; and transmitting a PRECHARGE command and an ACTIVE command in advance. With the above technical solution, the PRECHARGE command and ACTIVE command which should have been transmitted serially can be transmitted in advance by being hidden in parallel in a Read or WRITE period to thereby make full use of a bandwidth of a DDR device.Type: GrantFiled: July 25, 2011Date of Patent: June 20, 2017Assignee: ARTEK Microelectronics Co., Ltd.Inventor: Hongbin Wang