Abstract: In an embodiment, a data processing method comprises implementing a memory event interface to a hypercall interface of a hypervisor or virtual machine operating system to intercept page faults associated with writing pages of memory that contain a computer program; receiving a page fault resulting from a guest domain attempting to write a memory page that is marked as not executable in a memory page permissions system; determining a first set of memory page permissions for the memory page that are maintained by the hypervisor or virtual machine operating system; determining a second set of memory page permissions for the memory page that are maintained independent of the hypervisor or virtual machine operating system; determining a particular memory page permission for the memory page based on the first set and the second set; processing the page fault based on the particular memory page permission, including performing at least one security function associated with regulating access of the guest domain to th

Abstract: A method is used in mapping data storage and virtual machines. A logical volume from a data storage system is provided for use by a hypervisor. The hypervisor is queried through a web service to identify a virtual machine of the hypervisor. It is determined that the virtual machine is using the logical volume.

Abstract: Disclosed is an information storing device which includes a first interface for connection with a host; a second interface for connection with the host; a first memory unit including a first controller controlling a first nonvolatile memory, the first controller communicating with the host via the first interface; and a second memory unit including a second controller controlling a second nonvolatile memory, the second controller communicating with the host via the second interface.

Abstract: Multiple segment operations having non-volatile state trackers in memory devices are disclosed. Operations are segmented in multiple segments and selectively performed to avoid violating timing requirements within a memory device. In at least one embodiment, a memory device operation is segmented into a plurality of segments and selectively performed within time frames of other memory device operations. Non-volatile state trackers maintain state values corresponding to each segment of multiple segmented operations.

Abstract: Techniques for utilizing flash storage as an extension of hard disk (HDD) based storage are provided. In one embodiment, a computer system can store a first subset of blocks of a logical file in a first physical file residing on a flash storage tier, and a second subset of blocks of the logical file in a second physical file residing on an HDD storage tier. The computer system can then receive an I/O request directed to one or more blocks of the logical file and process the I/O request by accessing the flash storage tier or the HDD storage tier, the accessing being based on whether the one or more blocks are part of the first subset of blocks stored in the first physical file.

Abstract: A virtual tape device includes a storage unit, a cache determining unit, a selector, and a cache controller. The storage unit records logical volume information associated with an identifier of a logical volume, an updated time of the logical volume, information indicating whether the logical volume is allocated to a cache, an identifier of a physical volume storing data of the logical volume, and information indicating whether the physical volume are mounted in a physical tape drive. The cache determining unit determines, based on the logical volume information, whether the logical volume exists on the cache, when a request to store the logical volume on the cache is received and the cache does not have an available capacity. The selector selects the logical volume based on the determined result as an off-cache target logical volume. The selected logical volume is off-cached by the cache controller.

Abstract: Solid state storage devices and methods for flash translation layers are disclosed. In one such translation layer, a sector indication is translated to a memory location by a parallel unit look-up table is populated by memory device enumeration at initialization. Each table entry is comprised of communication channel, chip enable, logical unit, and plane for each operating memory device found. When the sector indication is received, a modulo function operates on entries of the look-up table in order to determine the memory location associated with the sector indication.

Abstract: A first storage system comprises a first logical volume, and a first controller that has a first memory. A second storage system comprises a second physical storage device that constitutes the basis of a second logical volume and a journal area, and a second controller that has a second memory. At least the first memory stores a write unit size, which is the size of a write data element. The journal area is a storage area in which is stored a journal data element, which is a data element that is stored in any block of a plurality of blocks configuring the first and/or second logical volume, or a data element that is written to this block. The size of the journal data element, and the size of the respective blocks that are managed as the respective components of the first and second logical volumes are the write unit size.

Abstract: A computer system using virtual memory provides hybrid memory access either through a conventional translation between virtual memory and physical memory using a page table possibly with a translation lookaside buffer, or a high-speed translation using a fixed offset value between virtual memory and physical memory. Selection between these modes of access may be encoded into the address space of virtual memory eliminating the need for a separate tagging operation of specific memory addresses.

Abstract: Systems and methods are provided for a content addressable memory. A system includes a common memory module configured to store a plurality of entries, ones of the entries being defined by a string of bits. A first parallel compare logic unit is configured to compare a first lookup key against a plurality of entries stored in the memory module in a first memory operation cycle and to output a match indication indicating a match between the first lookup key and the string of bits of an entry from among the plurality of entries. A second parallel compare logic unit is configured to compare, in the first memory operation cycle, a second lookup key against the plurality of entries stored in the memory module and to output a match indication indicating a match between the second lookup key and the string of bits of an entry from among the plurality of entries.

Abstract: A transactional memory system predicts the outcome of coalescing outermost memory transactions, the coalescing causing committing of memory store data to memory for a first transaction to be done at transaction execution (TX) end of a second transaction, the method comprising. A processor of the transactional memory system determines whether a first plurality of outermost transactions from an associated program that were coalesced experienced an abort, the first plurality of outermost transactions including a first instance of a first transaction. The processor updates a history of the associated program to reflect the results of the determination. The processor coalesces a second plurality of outermost transactions from the associated program, based, at least in part, on the updated history.

Abstract: In one embodiment, a method includes storing data received from at least two data sources in a buffer, writing the data from the at least two data sources to regions in a first wrap of a tape on a data-source basis in a first predetermined order, and writing the data from the at least two data sources to regions in the second wrap in a second predetermined order, the second predetermined order being a reverse order relative to the first predetermined order.

Abstract: Systems and methods of writing data to a buffer during a buffer cycle are described. The buffer has a plurality of buffer banks having various fill levels. The buffer determines a first portion of banks from the plurality of buffer banks. The first portion of banks unfilled banks. A rank can be assigned to each of the first portion of banks and a candidate set of banks chosen from the first portion of banks. A target bank is then chosen from the candidate set and the data is written to that bank. The ranking may be random. Furthermore, the target bank can be chosen based on ranking, fill level, or both.

Abstract: Methods, systems, and products for computer processing. In one general embodiment, the method comprises running an inner process in the context of an executing thread wherein the thread has an original address space in memory and hiding at least a portion of the memory from the inner process. The inner process may run on the same credentials as the thread. Running the inner process may include creating a new address space for the inner process in the memory and assigning the new address space to the thread, so that the inner process comprises its own address space. The inner process may he allowed to access only the new address space. The kernel may maintain the thread's original address space along with the new address space, so that multiple address spaces exist for a particular thread. The kernel may pass selected data from the thread to the inner process.

Abstract: A virtual tape device includes a memory to record logical volume information that includes an identifier of a logical volume, an identifier of a physical volume that stores data of the logical volume, and information that indicates whether the data of the logical volume is cached in a cache unit, in association with each other. A determining unit that, when a copy command to copy data of the logical volume stored in a first physical volume to a second physical volume is received, determines whether a logical volume cached in the cache unit exists among the logical volumes, and a storage control unit that, when it is determined that the logical volume cached in the cache unit exists among the logical volumes, stores the data of the logical volume cached in the cache unit to the second physical volume without reference to an order indicated in the copy command.

Abstract: Aspects of virtual one-time programmable (OTP) memory pre-programming are described. A device may include a logical sink destination, an OTP memory map, a virtual memory map, and a comparator. The OTP memory map may store one or more OTP logical values, and the virtual memory map may store one or more default virtual logical values. Generally, the virtual memory map may be predefined for various representative OTP scenarios including test and customer-specific values. Certain portions or outputs of the logical values stored in the OTP memory map and the virtual memory map may be compared by the comparator, and the logical result of the comparison may be output to the logical sink destination. In certain aspects, the portions or outputs of OTP and virtual memory maps that are compared may be determined based on various factors such as strap option settings, temperatures, voltages, or register values of the device.

Abstract: According to one embodiment, in response to a request to write a prime segment of a file system of a storage system, one or more of the storage units are identified based on a prime segment write-map (PSWM). The PSWM includes storage unit identifiers (IDs) identifying the storage units to which a new prime segment should be written. The prime segment is then written in the one or more storage units identified from the PSWM, without writing the prime segment to a remainder of the storage units. The first prime segment is one of a plurality of prime segments collectively representing a prime. The prime contains metadata representing a consistent point of data stored in the file system, including a reference to a root of the file system. The first prime segment can be utilized to restore the file system back to a state represented by the consistent point.

Abstract: A NAND Flash based content addressable memory (CAM) is used for a key-value addressed storage drive. The device can use a standard transport protocol such as PCI-E, SAS, SATA, eMMC, SCSI, and so on. A host writes a key-value pair to the drive, where the drive writes the keys along bit lines of a CAM NAND portion of the drive and stores the value in the drive. The drive then maintains a table linking the keys to location of the value. In a read process, the host provides a key to drive, which then broadcasts down the word lines of blocks storing the keys. Based on any matching bit lines, the tables can then be used to retrieve and supply the corresponding data to the host.

Abstract: Shared storage architectures and methods are provided. A particular shared storage architecture is a system including shared storage including data and file system metadata separated from the data. The file system metadata includes location data specifying storage location information related to the data. Services are provided from service providers to service consumers through the shared storage.

Abstract: A method of operation of an electronic system includes: forming a superblock by organizing an erase block according to a wear attribute; detecting a trigger count of the wear attribute of the superblock; updating a metadata table with the trigger count; and triggering a recycling event of the superblock based on the metadata table.