Patents Examined by Craig Goldschmidt
  • Patent number: 8769201
    Abstract: A technique to enable resource allocation optimization within a computer system. In one embodiment, a gradient partition algorithm (GPA) module is used to continually measure performance and adjust allocation to shared resources among a plurality of data classes in order to achieve optimal performance.
    Type: Grant
    Filed: December 2, 2008
    Date of Patent: July 1, 2014
    Assignee: Intel Corporation
    Inventors: William Hasenplaugh, Joel Emer, Tryggve Fossum, Aamer Jaleel, Simon Steely
  • Patent number: 8762623
    Abstract: A method for managing a plurality of blocks of a Flash memory includes: sieving out at least one first block having invalid pages from the plurality of blocks; and moving data of a portion of valid pages of the first block to a second block, where data of all valid pages of the first block is not moved to the second block at a time. An associated memory device and a controller thereof are also provided, where the controller includes: a ROM arranged to store a program code; and a microprocessor arranged to execute the program code to control the access to the Flash memory and manage the plurality of blocks. The controller that executes the program code by utilizing the microprocessor sieves out the first block from the plurality of blocks, and moves the data of the portion of valid pages of the first block to the second block.
    Type: Grant
    Filed: October 27, 2009
    Date of Patent: June 24, 2014
    Assignees: Silicon Motion Inc., Silicon Motion Inc.
    Inventor: Chun-Kun Lee
  • Patent number: 8725948
    Abstract: A computer system caches variable-length instructions in a data structure. The computer system locates a first copy of an instruction in the cached data structure using a current value of the instruction pointer as a key. The computer system determines a predictive length of the instruction, and reads a portion of the instruction from an instruction memory as a second copy. The second copy has the predictive length. Based on the comparison of the first copy with the second copy, the computer system determines whether or not to read the rest of the instruction from the instruction memory, and then interprets the instruction for use by the computer system.
    Type: Grant
    Filed: October 6, 2010
    Date of Patent: May 13, 2014
    Assignee: Red Hat Israel, Ltd.
    Inventors: Michael Tsirkin, Uri Lublin
  • Patent number: 8719495
    Abstract: A method and apparatus are disclosed for concatenating a first RAID and a second RAID. The apparatus includes a concatenation module and a direction module. The concatenation module concatenates a first Redundant Array of Independent Disks (“RAID”) with a second RAID into a top-level RAID. The first RAID and the second RAID may have disparate operational characteristics. The direction module directs storage operations to one of the first RAID and the second RAID based on a direction policy.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: May 6, 2014
    Assignee: Lenovo (Singapore) PTE. Ltd.
    Inventors: Donald R. Frame, Jeffrey R. Hobbet, Kenneth Dean Timmons, Michael Scott Mettler
  • Patent number: 8713282
    Abstract: According to one embodiment, a large scale data storage system with fault tolerance is described. In one example, a system includes a plurality of storage partitions, each partition including a portion of a large scale data store, and metadata corresponding to the portion of the large scale data store. At least one partition includes namespace metadata for the large scale data store including namespace data for a portion of the large scale data store outside the at least one partition.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: April 29, 2014
    Assignee: EMC Corporation
    Inventors: Abhishek Rajimwale, Windsor W. Hsu
  • Patent number: 8707006
    Abstract: A method for managing a memory, including obtaining a number of indices and a cache line size of a cache memory, computing a cache page size by multiplying the number of indices by the cache line size, calculating a greatest common denominator (GCD) of the cache page size and a first size class, incrementing, in response to the GCD of the cache page size and the first size class exceeding the cache line size, the first size class to generate an updated first size class, calculating a GCD of the cache page size and the updated first size class, creating, in response to the GCD of the cache page size and the updated first size class being less than the cache line size, a first superblock in the memory including a first plurality of blocks of the updated first size class, and creating a second superblock in the memory.
    Type: Grant
    Filed: October 6, 2010
    Date of Patent: April 22, 2014
    Assignee: Oracle International Corporation
    Inventor: David Dice
  • Patent number: 8700860
    Abstract: An information processing apparatus for processing input data using multiple items of reference data in succession is provided. The apparatus includes a secondary storage unit configured to store the reference data; a primary storage unit accessible at a speed higher than that of the secondary storage unit; a read-out unit configured to read out the reference data from the secondary storage unit to the primary storage unit; an execution unit configured to execute processing of the input data using the reference data in the primary storage unit; a determination unit configured to determine, based upon at least one of a probability that reference data scheduled for use by the execution unit will change and quantity of the scheduled reference data, whether the scheduled reference data is to be prefetched; and a control unit configured to control prefetch based on the result of determination of the determination unit.
    Type: Grant
    Filed: October 6, 2010
    Date of Patent: April 15, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Ryoko Mise, Akiyoshi Momoi
  • Patent number: 8700851
    Abstract: A main memory stores cache blocks obtained by dividing a program. At a position in a cache block where a branch to another cache block is provided, an instruction is embedded for activating a branch resolution routine for performing processing, such as loading of a cache block of the branch target. A program is loaded into a local memory in units of cache blocks, and the cache blocks are serially stored in first through nth banks, which are sections provided in the storage area. Management of addresses in the local memory or processing for discarding a copy of a cache block is performed with reference to an address translation table, an inter-bank reference table, and a generation number table.
    Type: Grant
    Filed: March 19, 2008
    Date of Patent: April 15, 2014
    Assignees: Sony Corporation, Sony Computer Entertainment Inc.
    Inventor: Atsushi Togawa
  • Patent number: 8677076
    Abstract: The system described herein may track references to a shared object by concurrently executing threads using a reference tracking data structure that includes an owner field and an array of byte-addressable per-thread entries, each including a per-thread reference counter and a per-thread counter lock. Slotted threads assigned to a given array entry may increment or decrement the per-thread reference counter in that entry in response to referencing or dereferencing the shared object. Unslotted threads may increment or decrement a shared unslotted reference counter. A thread may update the data structure and/or examine it to determine whether the number of references to the shared object is zero or non-zero using a blocking-optimistic or a non-blocking mechanism. A checking thread may acquire ownership of the data structure, obtain an instantaneous snapshot of all counters, and return a value indicating whether the number of references to the shared object is zero or non-zero.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: March 18, 2014
    Assignee: Oracle International Corporation
    Inventors: David Dice, Nir N. Shavit
  • Patent number: 8667236
    Abstract: A host write based write ordering mechanism is used so the write ordering on the secondary system is derived from the write ordering applied by the host to the primary system. In this scheme any set of writes that was issued in parallel on the primary system may also be issued in parallel on the secondary system. The parallel writes provide better performance compared to absolute or strict write ordering allowing only one outstanding write per volume group.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: March 4, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Adam M. Phelps, Richard T. Dalzell, Hariprasad Mankude Bhasker Rao
  • Patent number: 8656093
    Abstract: One embodiment of the invention sets forth a mechanism to transmit commands received from an L2 cache to a bank page within the DRAM. An arbiter unit determines which commands from a command sorter to transmit to a command queue. An activate command associated with the bank page related to the commands is also transmitted to an activate queue. The last command in the command queue is marked as “last.” An interlock counter stores a count of “last” commands in the read/write command queue. A DRAM controller transmits activate and commands from the activate queue and the command queue to the DRAM. Each time a command marked as “last” is encountered, the DRAM controller decrements the interlock counter. If the count in the interlock counter is zero, then the command marked as “last” is marked as “auto-precharge.” The “auto-precharge” command, when processed, causes the bank page to be closed.
    Type: Grant
    Filed: December 1, 2008
    Date of Patent: February 18, 2014
    Assignee: NVIDIA Corporation
    Inventors: John H. Edmondson, Shane Keil
  • Patent number: 8639877
    Abstract: A computational device allocates a plurality of solid state disks to a plurality of redundant array of independent disk (RAID) ranks, wherein a different solid state disk is absent in each RAID rank of the plurality of RAID ranks. The computational device determines at least one selected solid state disk from the plurality of solid state disks, wherein the at least one selected solid state disk is estimated to have undergone a greater amount of wear in comparison to other solid state disks in the plurality of solid state disks. Relatively more data and parity information is written to those RAID ranks in which the at least one selected solid state disk is absent in comparison to those RAID ranks in which the at least one selected solid state disk is present.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: January 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Michael Thomas Benhase, Andrew Dale Walls
  • Patent number: 8635422
    Abstract: A computer-implemented method for reclaiming storage space from deleted volumes on thin-provisioned disks may include: 1) identifying a deleted volume, 2) identifying storage space on a thin-provisioned disk that was allocated to the deleted volume, 3) saving information that identifies the storage space, 4) identifying a policy that specifies reclaiming the storage space asynchronously with respect to the deleted volume, and then 5) reclaiming the storage space asynchronously with respect to deletion of the volume in accordance with the policy. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Grant
    Filed: October 29, 2009
    Date of Patent: January 21, 2014
    Assignee: Symantec Corporation
    Inventors: Kirubakaran Kaliannan, Michael E. Root
  • Patent number: 8631206
    Abstract: Set-associative caches having corresponding methods and computer programs comprise: a data cache to provide a plurality of cache lines based on a set index of a virtual address, wherein each of the cache lines corresponds to one of a plurality of ways of the set-associative cache; a translation lookaside buffer to provide one of a plurality of way selections based on the set index of the virtual address and a virtual tag of the virtual address, wherein each of the way selections corresponds to one of the ways of the set-associative cache; and a way multiplexer to select one of the cache lines provided by the data cache based on the one of the plurality of way selections.
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: January 14, 2014
    Assignee: Marvell International Ltd.
    Inventors: R. Frank O'Bleness, Sujat Jamil, David E. Miner, Joseph Delgross, Tom Hameenanttila
  • Patent number: 8627011
    Abstract: Provided is a method for managing metadata for data in a copy relationship copied from a source storage to a target storage. Information is maintained on a copy relationship of source data in the source storage and target data in the target storage. The source data is copied from the source storage to the cache to copy to target data in the target storage indicated in the copy relationship. Target metadata is generated for the target data comprising the source data copied to the cache. An access request to requested target data comprising the target data in the cache is processed and access is provided to the requested target data in the cache. The target metadata for the requested target data in the target storage is discarded in response to determining that the requested target data in the cache has not been destaged to the target storage.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: January 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Michael T. Benhase, Theresa M. Brown, Lokesh M. Gupta, Suguang Li, Mark L. Lipets, Carol S. Mellgren, Kenneth W. Todd
  • Patent number: 8621133
    Abstract: A disk drive comprising a rotatable disk, a head configured to read data from the disk, and a controller is disclosed. The controller is configured to read a plurality of track metadata files from the disk during one revolution of the disk using the head, wherein each track metadata file defines logical address to physical address mapping for a track of the disk, each track metadata file is located on a different track of the disk, and the track metadata files are located at track locations such that one of the track metadata files is read shortly after a track-to-track seek from a previous track.
    Type: Grant
    Filed: June 29, 2010
    Date of Patent: December 31, 2013
    Assignee: Western Digital Technologies, Inc.
    Inventor: William B. Boyle
  • Patent number: 8615624
    Abstract: A method, apparatus, and computer program product are provided for enhancing memory erase functionality. An apparatus may include a block-based mass memory and a controller configured to receive an erase command from a host device comprising an indication of a location of a block in the mass memory storing memory allocation data. The controller may be further configured to access the memory allocation data based at least in part upon the indicated location. The controller may additionally be configured to determine, based at least in part upon the memory allocation data, blocks within the mass memory that have been freed by the host device. The controller may also be configured to erase the freed blocks. Corresponding methods and computer program products are also provided.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: December 24, 2013
    Assignee: Core Wireless Licensing S.A.R.L.
    Inventor: Olli Olavi Luukkainen
  • Patent number: 8595416
    Abstract: A method, computer program product, and computing system for identifying a low-write-frequency portion of a solid-state storage device. If it is determined that the low-write-frequency portion is of sufficient size to function as over-provisioning space for the solid-state storage device, the low-write-frequency portion is utilized as over-provisioning space.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: November 26, 2013
    Assignee: EMC Corporation
    Inventors: Patrick J. Weiler, James Guyer
  • Patent number: 8583866
    Abstract: Data storage reliability is maintained in a write-back distributed data storage system including multiple nodes. Information is stored as a stripe including a collection of a data strips and associated parity strips, the stripe distributed across data and parity nodes. Each data node maintains the data strip holding a first copy of data, and each parity node maintains a parity strip holding a parity for the collection of data strips. A driver node initiates a full-stripe-write parity update protocol for maintaining parity coherency in conjunction with other nodes, to keep the relevant parity strips coherent. Parity is determined directly by computing parity strips for all data strips of a stripe. Any node may function as a driver node.
    Type: Grant
    Filed: February 22, 2010
    Date of Patent: November 12, 2013
    Assignee: International Business Machines Corporation
    Inventors: David D. Chambliss, James L. Hafner, Tarun Thakur
  • Patent number: 8578094
    Abstract: Data storage reliability is maintained in a write-back distributed data storage system including multiple nodes. Information is stored as a stripe including a collection of a data strips and associated parity strips, the stripe distributed across data and parity nodes. Each data node maintains the data strip holding a first copy of data, and each parity node maintains a parity strip holding a parity for the collection of data strips. A driver node initiates a full-stripe-write parity update protocol for maintaining parity coherency in conjunction with other nodes, to keep the relevant parity strips coherent. Parity is determined directly by computing parity strips for all data strips of a stripe. Any node may function as a driver node.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: November 5, 2013
    Assignee: International Business Machines Corporation
    Inventors: David D. Chambliss, James L. Hafner, Tarun Thakur