Abstract: A computer-implemented method for creating space-saving snapshots may include: 1) identifying a parent volume on which to perform a snapshot, 2) allocating at least one thin-provisioned volume for the snapshot, 3) identifying an attempt to write to a region of the parent volume, and then 4) copying the region to the thin-provisioned volume. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A computer-implemented method for reclaiming storage space on striped volumes may include: 1) identifying a volume striped across a set of storage devices, 2) identifying a reclamation request to reclaim storage space allocated to the striped volume and then, for at least one device in the set of storage devices, 3) identifying stripes of storage on the device that are covered by the reclamation request, 4) creating a consolidated reclamation request for the device that identifies each stripe of storage on the device that is covered by the reclamation request, and then 5) issuing the consolidated reclamation request to the device. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A system and method for buffering intermediate data in a processing pipeline architecture stores the intermediate data in a shared cache that is coupled between one or more pipeline processing units and an external memory. The shared cache provides storage that is used by multiple pipeline processing units. The storage capacity of the shared cache is dynamically allocated to the different pipeline processing units as needed, to avoid stalling the upstream units, thereby improving overall system throughput.

Abstract: A first acquisition unit acquires each of the resources defined by the scenario, from locations depending on identifiers of the resources. A judging unit judge, when a resource having same identifier and structure as the resource acquired is existent in the cache storage, erases the resource, the identifier thereof, and the receipt time information from the cache storage, and when not existent, stores the acquired resource in association with the identifier thereof and the receipt time information of the bookmark instruction, in the cache storage. A second acquisition, when the identifiers of the resources specified by a first scenario are existent in the cache storage, acquires the resources from the cache storage according to the receipt time information corresponding to the first scenario and identifiers of the resources, and when not existent, acquires the resources from a location depending on the identifiers.

Abstract: The technique introduced here involves using a block address and a corresponding generation number as a “fingerprint” to uniquely identify a sequence of data within a given storage domain. Each block address has an associated generation number which indicates the number of times that data at that block address has been modified. This technique can be employed, for example, to maintain cache coherency among multiple storage nodes. It can also be employed to avoid sending the data to a network node over a network if it already has the data.

Abstract: Methods and apparatus for instruction restarts and inclusion in processor micro-op caches are disclosed. Embodiments of micro-op caches have way storage fields to record the instruction-cache ways storing corresponding macroinstructions. Instruction-cache in-use indications associated with the instruction-cache lines storing the instructions are updated upon micro-op cache hits. In-use indications can be located using the recorded instruction-cache ways in micro-op cache lines. Victim-cache deallocation micro-ops are enqueued in a micro-op queue after micro-op cache miss synchronizations, responsive to evictions from the instruction-cache into a victim-cache. Inclusion logic also locates and evicts micro-op cache lines corresponding to the recorded instruction-cache ways, responsive to evictions from the instruction-cache.

Abstract: A technique enables creation and use of a writable, read-only snapshot of an active file system operating on a storage system, such as a multi-protocol storage appliance. The writable, read-only snapshot comprises a read-only “image” (file) residing in a snapshot and a writable virtual disk (vdisk) residing in the active file system. The writable vdisk is a “shadow” image of the snapshot file image and, as such, includes an attribute that specifies the snapshot file as a backing store.

Abstract: A method, apparatus, and computer program product are provided for enhancing memory erase functionality. An apparatus may include a block-based mass memory and a controller configured to receive an erase command from a host device comprising an indication of a location of a block in the mass memory storing memory allocation data. The controller may be further configured to access the memory allocation data based at least in part upon the indicated location. The controller may additionally be configured to determine, based at least in part upon the memory allocation data, blocks within the mass memory that have been freed by the host device. The controller may also be configured to erase the freed blocks. Corresponding methods and computer program products are also provided.

Abstract: One embodiment of the present invention sets forth a technique for efficiently and flexibly performing coalesced memory accesses for a thread group. For each read application request that services a thread group, the core interface generates one pending request table (PRT) entry and one or more memory access requests. The core interface determines the number of memory access requests and the size of each memory access request based on the spread of the memory access addresses in the application request. Each memory access request specifies the particular threads that the memory access request services. The PRT entry tracks the number of pending memory access requests. As the memory interface completes each memory access request, the core interface uses information in the memory access request and the corresponding PRT entry to route the returned data.

Abstract: One embodiment of the invention sets forth a mechanism to transmit commands received from an L2 cache to a bank page within the DRAM. An arbiter unit determines which commands from a command sorter to transmit to a command queue. An activate command associated with the bank page related to the commands is also transmitted to an activate queue. The last command in the command queue is marked as “last.” An interlock counter stores a count of “last” commands in the read/write command queue. A DRAM controller transmits activate and commands from the activate queue and the command queue to the DRAM. Each time a command marked as “last” is encountered, the DRAM controller decrements the interlock counter. If the count in the interlock counter is zero, then the command marked as “last” is marked as “auto-precharge.” The “auto-precharge” command, when processed, causes the bank page to be closed.

Abstract: A technique migrates data from source arrays to target arrays. The array devices operate in either active mode, passive mode, or stalled-active mode. The technique involves providing active-to-passive instructions to transition the source devices from active to passive while a host initially accesses host data from the source arrays using MPIO software (the target devices being in stalled-active mode), and monitoring whether the source devices successfully transition to passive during a predefined time period. If so, the technique involves operating the target devices in active mode and transferring data from the source devices to the target devices to enable the host to access the host data from the target arrays using the MPIO software. However, if a source device remains passive, the technique involves providing passive-to-active instructions to transition the source devices back to active to enable the host to access the host data from the source arrays.

Abstract: Testing a circuit in a post-silicon stage is performed by enabling the different processing entities of the circuit to determine a consistent access permissions schema in a random manner. Based upon the consistent access permissions schema, addresses to be accessed during the testing of the circuit may be determined. The addresses may be determined in a random manner. The consistent permissions schema may be determined based on a template representative of repetitive portions of access permissions schema. The disclosed subject matter may utilize biasing modules to bias the test generation to provide a test having a predetermined characteristic. The disclosed subject matter may utilize a joint random seed or other techniques to provide for consistent random decisions by the different processing entities.

Abstract: A source system comprises memory and a processor executing code to cause at least some of the memory to be migrated over a network to a target system. The processor causes the memory to be migrated by migrating some of the memory while a guest continues to write the memory, halts execution of the guest, and completes a remainder of the memory migration.

Abstract: A memory system includes a nonvolatile memory having a plurality of data blocks each of which is a unit of data erase and has a plurality of pages, each of the pages being a unit of data write, and a controller which checks whether or not the nonvolatile memory has been affected by power interruption at power-on time and, if the nonvolatile memory has been affected by power interruption, writes data to that first page in a first data block which has not been affected by power interruption.

Abstract: This invention is a system and a method for operating a storage server in a data network using a new architecture. The method of creating the partial block map allows the snapshot writes on a direct mapped file. The method of reading data or writing data to the file created in direct mapping state and later converted to partial mapping state responsive to a copy on first write request by a client allocates new indirect block when needed to store the reference to newly allocated data block. The method of reading data from or writing data to the file in partial mapping state involves checking the mapping bit to find if the indirect block is in direct mapping state.

Abstract: In a distributed RAID-1 (DR1) copy operation, operation of source and target DR1 volumes is first converted to a local-copy operating mode in which the distributed copy operation is converted into a set of local copy operations. Each t is performed at a respective location of the disks of the DR1 volumes and involves copying data of the source DR1 from a first disk to a second disk via a local second communication channel of relatively high bandwidth. Following conversion, the local copy operations are performed at the locations. Upon completion of the local copy operations, storage operations to the source and target DR1 volumes are temporarily suspended, operation of the source and target DR1 volumes is converted back to the normal operating mode, and storage operations to the source and target DR1 volumes are resumed.

Abstract: A information processing apparatus includes, upon instructing for writing back stored contents of a main memory unit to the stored contents of the main memory unit at the time of previous modification in a sequence number that is used for identifying whether write back to the main memory unit is needed, from a backup data stored in a backup memory unit, the sequence number stored in a sequence number memory unit. The information processing apparatus selects the backup data including an integrity verification data indicating that writing is carried out completely. The information processing apparatus extracts an original data and a write destination address included in the selected backup data and writes the original data, for each original data and the write address extracted from the backup data, to a storage area, of the main memory unit, indicated by the write destination address.

Abstract: Disclosed is a method of issuing volume level alerts to provide a warning that indicates overutilization of storage resources in a computer system. Volume level checking is performed without the necessity of checking all the volumes, but only upon the occurrence of certain changes so that the only the most problematic volumes are checked. Hence, only a small number of volumes must be checked and only in response to certain identified changes. The method is applicable to any criterion for overutilization of storage resources which satisfies basic persistency rules. The method is also applicable to assessing risk for the use of other resources, such as communication bandwidth, that are supplied by resource providers, or pools of providers, to users of bandwidth. The principles disclosed can be utilized to check resources on an asset by asset basis, using the free space ratio definition provided to assess risk of overutilization of resources.

Abstract: Incrementing sequence numbers in the metadata of non-volatile memory is used in the event of a resume from power fail to determine which data in the memory is current and valid, and which data is not. To reduce the amount of metadata space consumed by these sequence numbers, the numbers are permitted to be small enough to wrap around when the maximum value is reached. Two different techniques are disclosed to keep this wrap around condition from causing ambiguity in the relative values of the sequence numbers.

Abstract: A cache memory logically partitions a cache array having a single access/command port into at least two slices, and uses a first directory to access the first array slice while using a second directory to access the second array slice, but accesses from the cache directories are managed using a single cache arbiter which controls the single access/command port. In one embodiment, each cache directory has its own directory arbiter to handle conflicting internal requests, and the directory arbiters communicate with the cache arbiter. The cache array is arranged with rows and columns of cache sectors wherein a cache line is spread across sectors in different rows and columns, with a portion of the given cache line being located in a first column having a first latency and another portion of the given cache line being located in a second column having a second latency greater than the first latency.