Abstract: A semiconductor device includes first and second metal layers, a dielectric layer, first, second, and third semiconductor regions, a first control electrode, and a first electrode. The dielectric layer is located on the first metal layer. The second metal layer is located on the dielectric layer, and electrically connected with the first metal layer. The first semiconductor region is located on the second metal layer and electrically connected with the second metal layer. The second semiconductor region is located on the first semiconductor region. The third semiconductor region is located on the second semiconductor region. The first control electrode faces the second semiconductor region via a first insulating film. The first electrode is located on the third semiconductor region and the first control electrode, electrically connected with the third semiconductor region, and insulated from the first control electrode by a first insulating portion.

Abstract: A super junction semiconductor device includes a substrate of a first conductive type, an epitaxial layer disposed on the substrate, a plurality of pillars extending in a vertical direction and each being alternately arranged within the epitaxial layer, gate structures disposed on the epitaxial layer in the active region, a reverse recovery layer of a second conductive type, the reverse recovery layer disposed on both the pillars and the epitaxial layer and in the transition region to distribute a reverse recovery current, and at least one high concentration region surrounding an upper portion of at least one of the pillars in the peripheral region, the high concentration region having a horizontal width greater than that of one of the pillars provided in the transition region. Thus, a breakdown voltage may be inhibited from decreasing in the peripheral region.

Abstract: A display apparatus including a substrate including a display area and a sensor area, the sensor area including a transmission portion that transmits light, a plurality of first display devices arranged in the display area, a display device group including a plurality of second display devices, the display device group being arranged in the sensor area, and a passivation layer covering the display device group and having a first hole corresponding to the transmission portion.

Abstract: A semiconductor device includes a through-substrate via extending from a frontside to a backside of a semiconductor substrate. The through-substrate via includes a concave or a convex portion adjacent to the backside of the semiconductor substrate. An isolation film is formed on the backside of the semiconductor substrate. A conductive layer includes a first portion formed on the concave or convex portion of the through substrate via and a second portion formed on the isolation film. A passivation layer partially covers the conductive layer.

Abstract: In an embodiment, a device includes: a first fin extending from a substrate; a gate stack disposed on the first fin; a source/drain region disposed in the first fin; a contact etch stop layer (CESL) disposed over the source/drain region; a gate spacer extending along a side of the gate stack; and a dielectric plug disposed between the CESL and the gate spacer, where the dielectric plug, the CESL, the gate spacer, and the source/drain region collectively define a void physically separating the gate stack from the source/drain region.

Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, a conductive member, a semiconductor member, and an insulating member. The second electrode includes a conductive portion. The conductive portion is between the third electrode and the conductive member. The conductive member is electrically connected with the second electrode. The semiconductor member includes first to third semiconductor regions. The second semiconductor region is between the third semiconductor region and a portion of the first semiconductor region. The second semiconductor region is between the third electrode and the conductive member. The conductive portion is electrically connected with the second and third semiconductor regions. The first electrode is electrically connected with the first semiconductor region. At least a portion of the first insulating member is between the semiconductor member and the third electrode and between the semiconductor member and the first conductive member.

Abstract: An object of a technique of the present disclosure is to suppress reduction in withstand voltage in a power semiconductor device. A semiconductor base includes an n? type semiconductor substrate and at least one p type diffusion layer formed separately from each other on a surface layer on a side of a first main surface of the semiconductor substrate in a terminal region. A power semiconductor device includes at least one insulating film formed on a first main surface of the semiconductor base between an insulating film and the insulating film. A semi-insulating film has contact with the insulating film on the insulating film, and has contact with the first main surface in at least two regions where the insulating film is not formed between the insulating films.

Abstract: A silicon carbide semiconductor device includes silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of the first conductivity type, a third semiconductor layer of a second conductivity type, a first semiconductor region of the first conductivity type, a trench, a gate insulating film, a gate electrode, and an interlayer insulating film. The first semiconductor layer and the second semiconductor layer constitute a first-conductivity-type semiconductor layer and in a deep region of the first-conductivity-type semiconductor layer at least 1 ?m from an interface with the third semiconductor layer, a maximum value of a concentration of aluminum is less than 3.0×1013/cm3. In the deep region of the first-conductivity-type semiconductor layer, a maximum value of a concentration of boron is less than 1.0×1014/cm3.

Abstract: In a general aspect, a semiconductor device can include a substrate of a first conductivity type, an active region disposed in the substrate, and a termination region disposed in the substrate adjacent to the active region. The termination region can include a junction termination extension (JTE) of a second conductivity type, where the second conductivity type is opposite the first conductivity type. The JTE can have a first depletion stopper region disposed in an upper portion of the JTE, a second depletion stopper region disposed in a lower portion of the JTE, and a high carrier mobility region disposed between the first depletion stopper region and the second depletion stopper region.

Abstract: Embodiments of the invention include a vertical field-effect transistor (VTFET) inverter. The VTFET inverter may include a p-channel field-effect transistor (P-FET) with a P-FET top source/drain and a P-FET bottom source/drain. The VTFET inverter may also include an n-channel field-effect transistor (N-FET) comprising an N-FET top source/drain and a N-FET bottom source/drain. The VTFET inverter may also include a buried contact located at a boundary between the P-FET bottom source/drain and the N-FET bottom source/drain. The VTFET inverter may also include a Vout contact electrically connected to one of the P-FET bottom source/drain and the N-FET bottom source/drain.

Abstract: Methods for fabricating SiC MOSFETs using channeled ion implants are disclosed. By aligning the workpiece such that the ions pass through channels in the SiC hexagonal crystalline structure, it is possible to achieve deeper implants than are otherwise possible. Further, it was found that these channeled implants can be tailored to achieve box-like dopant concentrations. This allows channeled ion implants to be used to create the current spreading layer of the MOSFET, which is conventional fabricated using epitaxial growth. Further, these channeled implants can also be used to create the shields between adjacent transistors. Additionally, the use of channeled implants allows a reduction in the number of epitaxially growth processes that are used to create super junction MOSFETs.

Abstract: Integrated circuit structures having source or drain structures with abrupt dopant profiles are described. In an example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires. The first and second epitaxial source or drain structures include silicon, phosphorous and arsenic, with an atomic concentration of phosphorous substantially the same as an atomic concentration of arsenic.

Abstract: A semiconductor device includes a semiconductor layer made of a wide bandgap semiconductor and including a gate trench; a gate insulating film formed on the gate trench; and a gate electrode embedded in the gate trench to be opposed to the semiconductor layer through the gate insulating film. The semiconductor layer includes a first conductivity type source region; a second conductivity type body region; a first conductivity type drift region; a second conductivity type first breakdown voltage holding region; a source trench passing through the first conductivity type source region and the second conductivity type body region from the front surface and reaching a drain region; and a second conductivity type second breakdown voltage region selectively formed on an edge portion of the source trench where the sidewall and the bottom wall thereof intersect with each other in a parallel region of the source trench.

Abstract: An electronic device includes a semiconductor body of silicon carbide, and a body region at a first surface of the semiconductor body. A source region is disposed in the body region. A drain region is disposed at a second surface of the semiconductor body. A doped region extends seamlessly at the entire first surface of the semiconductor body and includes one or more first sub-regions having a first doping concentration and one or more second sub-regions having a second doping concentration lower than the first doping concentration. Thus, the device has zones alternated to each other having different conduction threshold voltage and different saturation current.

Abstract: An LED package comprising a submount having a top and bottom surface with a plurality of top electrically and thermally conductive elements on its top surface. An LED is included on one of the top elements such that an electrical signal applied to the top elements causes the LED to emit light. The electrically conductive elements also spread heat from the LED across the majority of the submount top surface. A bottom thermally conductive element is included on the bottom surface of said submount and spreads heat from the submount, and a lens is formed directly over the LED. A method for fabricating LED packages comprising providing a submount panel sized to be separated into a plurality of LED package submounts. Top conductive elements are formed on one surface of the submount panel for a plurality of LED packages, and LEDs are attached to the top elements. Lenses are molded over the LEDs and the substrate panel is singulated to separate it into a plurality of LED packages.

Abstract: An organic image sensor may be configured to obtain a color signal associated with a particular wavelength spectrum of light absorbed by the organic image sensor may omit a color filter. The organic image sensor may include an organic photoelectric conversion layer including a first material and a second material. The first material may absorb a first wavelength spectrum of light, and the second material may absorb a second wavelength spectrum of light. The organic photoelectric conversion layer may include stacked upper and lower layers, and the respective material compositions of the lower and upper layers may be first and second mixtures of the first and second materials. A ratio of the first material to the second material in the first mixture may be greater than 1/1, and a ratio of the first material to the second material in the second mixture may be less than 1/1.

Abstract: A first main surface of a silicon carbide substrate is provided with a first trench and a second trench. The first trench is defined by a first side surface and a first bottom surface. The second trench is defined by a second side surface and a second bottom surface. The silicon carbide substrate includes a first impurity region, a second impurity region, a third impurity region, and a fourth impurity region. A first insulating film is in contact with each of the first side surface and the first bottom surface. A gate electrode is provided on the first insulating film. A second insulating film is in contact with each of the second side surface and the second bottom surface. The second impurity region has a connection region electrically connected to the fourth impurity region and extending toward the fourth impurity region along the second side surface.

Abstract: A semiconductor memory device includes a substrate, an active structure, a shallow trench isolation and a plurality of word lines. The active structure is disposed in the substrate, and includes a plurality of first active fragments and a plurality of second active fragments extended parallel to each other along a first direction and the second active fragments are disposed outside a periphery of all of the first active fragments. The shallow trench isolation is disposed in the substrate to surround the active structure, and which includes a plurality of first portions and a plurality of second portions. The word lines are disposed in the substrate, parallel with each other to extend along a second direction, wherein at least one of the word lines are only intersected with the second active fragments, or at least one of the word lines does not pass through any one of the second portions.

Abstract: A method for preparing a semiconductor device includes forming a ring structure over a semiconductor substrate, and etching the semiconductor substrate by using the ring structure as a mask to form an annular semiconductor fin. The method also includes epitaxially growing a first bottom source/drain structure within the annular semiconductor fin and a second bottom source/drain structure surrounding the annular semiconductor fin. The method further includes forming a first silicide layer over the first bottom source/drain structure and a second silicide layer over the second bottom source/drain structure. In addition, the method includes forming a first gate structure over the first silicide layer and a second gate structure over the second silicide layer, and epitaxially growing a top source/drain structure over the annular semiconductor fin.

Abstract: Image sensor structures are provided. The image sensor structure includes a substrate and a light-sensing region formed in the substrate. The image sensor structure further includes a first isolation structure surrounding the light sensing region and having an opening region in a top view and a second isolation structure formed in the substrate. In addition, the second isolation structure surrounds the light-sensing region and vertically overlaps both the opening region and the first isolation structure. The image sensor structure further includes a first gate structure formed over the substrate and overlapping the opening region, the first isolation structure, and the second isolation structure.