Abstract: An improved SiC trench MOSFET having first and second type gate trenches for formation of a gate electrode, and a grounded P-shield region under the gate electrode for gate oxide electric-field reduction is disclosed. The gate electrodes are disposed into the first type gate trench having a thick oxide layer on trench bottom. The grounded P-shield region surrounding the second type gate trench filled up with the thick oxide layer is connected with a source metal through a grounded P region. The device further comprises a current spreading region surrounding the first type gate trench for on-resistance reduction.

Abstract: At least one fin structure may be created on a silicon substrate. Next, a width of the at least one fin structure may be decreased by applying one or more iterations of a self-limiting fin etch process.

Abstract: A silicon carbide substrate is provided that includes a drift layer of a first conductivity type and a trench extending from a main surface of the silicon carbide substrate into the drift layer. First dopants are implanted through a first trench sidewall of the trench. The first dopants have a second conductivity type and are implanted at a first implant angle into the silicon carbide substrate, wherein at the first implant angle channeling occurs in the silicon carbide substrate. The first dopants form a first compensation layer extending parallel to the first trench sidewall.

Abstract: A method for creating at least one cavity in a semiconductor substrate including the steps of: (a) partially ablating the semiconductor substrate from the top side with a laser to form a trench in the semiconductor substrate surrounding a cross section of the semiconductor material having the desired shape, (b) machining the backside of the semiconductor substrate partially ablated in step (a) to reduce the semiconductor substrate to a final thickness that is equal to or less than the laser ablation depth to form a plug of semiconductor material unattached to a remainder of the semiconductor substrate; and (c) removing the plug of semiconductor material from the semiconductor substrate to form the at least one cavity with cross section of desired shape extending through the semiconductor substrate.

Abstract: A bonding wafer structure includes a support substrate, a bonding layer, and a silicon carbide (SiC) layer. The bonding layer is formed on a surface of the support substrate, and the SiC layer is bonded onto the bonding layer, in which a carbon surface of the SiC layer is in direct contact with the bonding layer. The SiC layer has a basal plane dislocation (BPD) of 1,000 ea/cm2 to 20,000 ea/cm2, a total thickness variation (TTV) greater than that of the support substrate, and a diameter equal to or less than that of the support substrate. The bonding wafer structure has a TTV of less than 10 ?m, a bow of less than 30 ?m, and a warp of less than 60 ?m.

Abstract: Semiconductor device packages include a redistribution layer (RDL) with carbon-based conductive elements. The carbon-based material of the RDL may have low electrical resistivity and may be thin (e.g., less than about 0.2 ?m). Adjacent passivation material may also be thin (e.g., less than about 0.2 ?m). Methods for forming the semiconductor device packages include forming the carbon-based material (e.g., at high temperatures (e.g., at least about 550° C.)) on an initial support wafer with a sacrificial substrate. Later or separately, components of a device region of the package may be formed and then joined to the initial support wafer before the sacrificial substrate is removed to leave the carbon-based material joined to the device region.

Abstract: A display panel is provided. The display panel according to an embodiment includes a thin film transistor glass substrate, a plurality of micro light emitting diodes (LEDs) arranged on one surface of the thin film transistor glass substrate, and a plurality of side wirings formed at an edge of the thin film transistor glass substrate to electrically connect the one surface of the thin film transistor glass substrate to an opposite surface to the one surface.

Abstract: A silicon carbide semiconductor device, including a semiconductor substrate, a first semiconductor layer provided on a first surface of the semiconductor substrate, a second semiconductor layer provided on a first surface of the first semiconductor layer, a third semiconductor layer provided on a first surface of the second semiconductor layer, a fourth semiconductor layer provided on a first surface of the third semiconductor layer, a plurality of first semiconductor regions of selectively provided in the fourth semiconductor layer at a first surface thereof, a gate electrode provided via a gate insulating film in the fourth semiconductor layer, between the first semiconductor regions and the third semiconductor layer, a first electrode provided on the first surface of the fourth semiconductor layer and surfaces of the first semiconductor regions, and a second electrode provided on a second surface of the semiconductor substrate.

Abstract: A method of forming a transistor structure is provided. The method includes forming on a substrate first and second mandrels for forming two-dimensional (2D) transistor fin elements defining a pitch gap region, depositing and anisotropically etching back the first spacer material to form first and second spacers in and around the first and second mandrels, respectively, conformally depositing and anisotropically etching back second spacer material around the first and second spacers and in the pitch gap region to define space for forming an odd number of one-dimensional (1D) transistor fin elements in the pitch gap region and depositing and anisotropically etching back the first spacer material in the space with enough cycles to fill the space to form a third spacer.

Abstract: An exemplary semiconductor device may include a substrate, an N? epitaxial layer positioned on the substrate, a first P region and a second P region positioned apart from each other on the N? epitaxial layer, a first N+ region positioned within the first P region, a second N+ region positioned within the second P region, and a gate layer positioned between the first P region and the second P region.

Abstract: A silicon carbide device includes a silicon carbide body having a hexagonal crystal lattice with a c-plane and with further main planes. The further main planes include a-planes and m-planes. A mean surface plane of the silicon carbide body is tilted to the c-plane by an off-axis angle. The silicon carbide body includes a columnar portion with column sidewalls. At least three of the column sidewalls are oriented along a respective one of the further main planes. A trench gate structure is in contact with the at least three of the column sidewalls.

Abstract: The present application discloses a semiconductor device with a graded porous dielectric structure. The semiconductor device includes a substrate; two conductive features positioned apart from each other over the substrate, a graded porous dielectric structure positioned between the two conductive features; and a dielectric layer positioned between one of the two conductive features and the graded porous dielectric structure; wherein the graded porous dielectric structure comprises a first portion having a first porosity and a second portion having a second porosity, and the second porosity is higher than the first porosity.

Abstract: Devices and methods are provided for forming single diffusion break isolation structures for integrated circuit devices including gate-all-around FET devices such as nanosheet FET devices and nanowire FET devices. For example, a semiconductor integrated circuit device includes first and second gate-all-around field-effect transistor devices disposed in first and second device regions, respectively, of a semiconductor substrate. A single diffusion break isolation structure is disposed between the first and second device regions. The single diffusion break isolation structure includes a dummy gate structure disposed on the semiconductor substrate between a first source/drain layer of the first gate-all-around field-effect transistor device and a second source/drain layer of the second gate all-around field-effect transistor device. The single diffusion break isolation structure is configured to electrically isolate the first and second source/drain layers.

Abstract: Techniques for the integration of SiGe/Si optical resonators with qubit and CMOS devices using structured substrates are provided. In one aspect, a waveguide structure includes: a wafer; and a waveguide disposed on the wafer, the waveguide having a SiGe core surrounded by Si, wherein the wafer has a lower refractive index than the Si (e.g., sapphire, diamond, SiC, and/or GaN). A computing device and a method for quantum computing are also provided.

Abstract: A semiconductor device and methods of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure disposed on the substrate, a source/drain (S/D) region disposed on the fin structure, and a gate structure disposed on the fin structure adjacent to the S/D region. The gate structure includes a gate stack disposed on the fin structure and a gate capping structure disposed on the gate stack. The gate capping structure includes a conductive gate cap disposed on the gate stack and an insulating gate cap disposed on the conductive gate cap. The semiconductor device further includes a first contact structure disposed over the gate stack. A portion of the first contact structure is disposed within the gate capping structure and is separated from the gate stack by a portion of the conductive gate cap.

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, first base regions of a second conductivity type, second base regions of the second conductivity type, a second semiconductor layer of the second conductivity type, first semiconductor regions of the first conductivity type, second semiconductor regions of the second conductivity type, gate insulating films, gate electrodes, an interlayer insulating film, first electrodes, a second electrode, and trenches. Between adjacent first base regions, at least two of the trenches, at least two of the gate electrodes, and at least two of the second base regions are disposed, the second base regions disposed between the adjacent first base regions being disposed separate from one another and separate from the first base regions, in a direction in which the trenches are arranged.

Abstract: The present disclosure provides a semiconductor structure, including a memory region, a logic region adjacent to the memory region, a first magnetic tunneling junction (MTJ) cell and a second MTJ cell over the memory region, and a carbon-based layer over the memory region, wherein the carbon-based layer includes a recess between the first MTJ cell and the second MTJ cell.

Abstract: A method of making a semiconductor device includes forming a first memory device, connecting a first word line to the first memory device, forming at least a first via, forming a second memory device, connecting a second word line to the second memory device, connecting a bit line to the first memory device and connecting the bit line to the second memory device by the first via. The first and second memory devices are separated by an inter-layer dielectric, and the first via connects the first memory device and the second memory device.

Abstract: The present invention provides a power device with super junction structure (or referred to as super junction power device) and a method of making the same. When making a super junction power device, impurity of a second conductive type may be implanted into an epitaxial layer of a first conductive type to form a floating island of the second conductive type and a pillar of the second conductive type successively through a super junction mask (or reticle) after forming the epitaxial layer of the first conductive type, directly through a well mask (or reticle) before or after forming a well of the second conductive type, and directly through a contact mask (or reticle) before or after forming a contact structure. Multiple epitaxial processes and deep trench etching process may not be needed. Therefore, the process is simple, the cost is low and yield and reliability are high.

Abstract: A method includes receiving a substrate having a front surface and a back surface; forming an isolation feature of a first dielectric material in the substrate, thereby defining an active region surrounded by the isolation feature; forming a gate stack on the active regions; forming a first and a second S/D feature on the fin active region; forming a front contact feature contacting the first S/D feature; thinning down the substrate from the back surface such that the isolation feature is exposed; selectively etching the active region, resulting in a trench surrounded by the isolation feature, the second S/D feature being exposed within the trench; forming, in the trench, a liner layer of a second dielectric material being different from the first dielectric material; forming a backside via feature landing on the second S/D feature within the trench; and forming a backside metal line landing on the backside via feature.