Abstract: A vertical non-volatile memory device includes a stack body including gate patterns and interlayer insulating patterns stacked in a stacking direction, the stack body having a through hole, which extends in the stacking direction, in the gate patterns and in the interlayer insulating patterns; a semiconductor pillar in the through hole and extending in the stacking direction; data storage structures between the gate patterns and the semiconductor pillar in the through hole, the data storage structures including charge storage layers; and dummy charge storage layers on a sidewall of the interlayer insulating patterns toward the semiconductor pillar in the through hole.

Abstract: Provided are a semiconductor device, a method of manufacturing the same, and a method of forming a uniform doping concentration of each semiconductor device when manufacturing a plurality of semiconductor devices. When a concentration balance is disrupted due to an increase in doping region size, doping concentration is still controllable by using ion blocking patterns to provide a semiconductor device with uniform doping concentration and a higher breakdown voltage obtainable as a result of such doping.

Abstract: Provided is an integrated circuit implemented by a plurality of vertical field effect transistors (VFETs) in one or more semiconductor cells, wherein a distance between a pair of second vertical channel structures of a first cell and an adjacent pair of first vertical channel structures in a second cell, all facing a cell boundary between the first and second cells, is the same as a distance between the pair of the first vertical channel structures and a pair of second vertical channel structures arranged next to the pair of the first vertical channel structures in the first cell.

Abstract: A device includes a substrate, and a first semiconductor channel over the substrate. The first semiconductor channel includes a first nanosheet of a first semiconductor material, a second nanosheet of a second semiconductor material in physical contact with a topside surface of the first nanosheet, and a third nanosheet of the second semiconductor material in physical contact with an underside surface of the first nanosheet. The first gate structure is over and laterally surrounding the first semiconductor channel, and in physical contact with the second nanosheet and the third nanosheet.

Abstract: An SiC semiconductor device includes an SiC semiconductor layer including an SiC monocrystal that is constituted of a hexagonal crystal and having a first main surface as a device surface facing a c-plane of the SiC monocrystal and has an off angle inclined with respect to the c-plane, a second main surface at a side opposite to the first main surface, and a side surface facing an a-plane of the SiC monocrystal and has an angle less than the off angle with respect to a normal to the first main surface when the normal is 0°.

Abstract: A semiconductor package includes a first semiconductor chip in which a through-electrode is provided, a second semiconductor chip connected to a top surface of the first semiconductor chip, a first connection bump attached to a bottom surface of the first semiconductor chip and including a first pillar structure and a first solder layer, and a second connection bump located between the first semiconductor chip and the second semiconductor chip, configured to electrically connect the first semiconductor chip and the second semiconductor chip, and including a second pillar structure and a second solder layer.

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, first semiconductor regions of the first conductivity type, second semiconductor regions of the second conductivity type, gate insulating films, gate electrodes, an insulating film, first electrodes, a second electrode, and trenches. The first semiconductor regions and the second semiconductor regions are periodically disposed apart from one another in a first direction in which the trenches extend in a stripe pattern.

Abstract: A process forms thin-film storage transistors (e.g., HNOR devices) with improved channel regions by conformally depositing a thin channel layer in a cavity bordering a source region and a drain region, such that a portion of the channel material abuts by junction contact the source region and another portion of the channel layer abut by junction contact the drain region. The cavity is also bordered by a storage layer. In one form of the process, the channel region is formed before the storage layer is formed. In another form of the storage layer is formed before the channel region is formed.

Abstract: A silicon carbide semiconductor device includes a silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, first semiconductor regions of the first conductivity type, trenches, a gate insulating film, gate electrodes, and an interlayer insulating film. The gate insulating film is formed by performing nitriding and oxidation by at least two sessions of a heat treatment by a mixed gas containing nitric oxide and nitrogen, the gate insulating film being configured by a first gate insulating film that is a silicon nitride layer, a second gate insulating film that is a silicon oxide film, and a third gate insulating film that is a silicon oxide film having a nitrogen area density lower than that of the second gate insulating film.

Abstract: A method used in forming an array of elevationally-extending strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. The stack comprises an etch-stop tier between a first tier and a second tier of the stack. The etch-stop tier is of different composition from those of the insulative tiers and the wordline tiers. Etching is conducted into the insulative tiers and the wordline tiers that are above the etch-stop tier to the etch-stop tier to form channel openings that have individual bases comprising the etch-stop tier. The etch-stop tier is penetrated through to extend individual of the channel openings there-through. After extending the individual channel openings through the etch-stop tier, etching is conducted into and through the insulative tiers and the wordline tiers that are below the etch-stop tier to extend the individual channel openings deeper into the stack below the etch-stop tier.

Abstract: A semiconductor memory device includes a first pillar. The first pillar includes a first portion and a second portion. The first portion includes a first semiconductor layer and a first insulating film on a side surface of the first semiconductor layer. The first pillar includes a first region that faces the first portion and a second region other than the first region. The second portion includes a first conductive film that is in contact with the first insulating film and a second insulating film. The second insulating film has a first thickness in a fourth direction within the second region and a second thickness in the second direction within the first region. The first thickness is greater than the second thickness.

Abstract: A MOS cell based on a simple and self-aligned process is provides a planar cell forming a horizontal MOS channel, and a plurality of trench regions, which are arranged at an angle with respect to the longitudinal direction of the planar cells. The new cell concept can adopt both planar MOS channels and Trench MOS channels in a single MOS cell structure, or planar MOS channels alone, while utilising the trenches to improve the current spreading of the planar MOS channels. Floating P-doped regions at the bottom of the trench regions protect the device against high peak electric fields. The orthogonal trench recesses are discontinued in their longitudinal direction to allow the planar channels to conduct electrons. The design can be applied to both IGBTs and MOSFETs based on silicon or wide bandgap materials.

Abstract: A base member for a light emitting device includes a bottom part and a frame part. The frame part has an upper surface, a lower surface, and a step portion. The frame part has a bonding surface bonded to the bottom part, and defining a planar surface of the step portion at a lower surface side, first and second inner surfaces, a first planar surface defining a planar surface of the step portion at an upper surface side, and first and second electrode layers electrically connected to each other, the second electrode layer being disposed on the first planar surface while the first electrode layer being not disposed on the first planar surface. The step portion extends along an entire periphery of the frame part in a bottom view, and the step portion does not extend along the entire periphery of the frame part in a top view.

Abstract: A semiconductor device includes a first MOS structure portion that includes, as its elements, a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a first second-semiconductor-layer of a second conductivity type, first semiconductor regions of the first conductivity type, and first gate insulating films, and a second MOS structure portion that includes, as its elements, the substrate, the first semiconductor layer, a second second-semiconductor-layer, second first-semiconductor-regions of the first conductivity type, and second gate insulating films. First and second portions include all of the elements of the first and second MOS structure portions other than the first and second first-semiconductor-regions and the first and second gate insulating films, respectively. A structure of one of the elements of the first portion is not identical to a structure of a corresponding element of the second portion.

Abstract: A wafer having a semiconductor substrate including a peripheral region and a central region, an insulating layer and a semiconductor layer is prepared first. Next, a plurality of trenches penetrating through the semiconductor layer and the insulating layer and reaching an inside of the semiconductor substrate are formed. Next, an inside of each of the plurality of trenches is filled with an insulating film, so that a plurality of element isolating portions is formed. Next, in the central region, the semiconductor layer exposed from a resist pattern is removed. The end portion closest to the outer edge of the semiconductor substrate among ends of the resist pattern used for removing the semiconductor layer in the central region is formed so as to be positioned closer to the outer edge of the semiconductor substrate than a position of the end portion closest to the outer edge of the semiconductor substrate among ends of the resist pattern used for forming the trenches.

Abstract: A semiconductor device including: a first structure including: a first semiconductor pattern protruding from a substrate, the first semiconductor pattern being a channel; a first conductive pattern surrounding the first semiconductor pattern, the first conductive pattern being a gate electrode; a first impurity region under the first semiconductor pattern, the first impurity region contacting the first semiconductor pattern, the first impurity region being a source or drain region; and a second impurity region contacting the first semiconductor pattern, the second impurity region being the other of the source or drain region; and a second structure including: second semiconductor patterns spaced apart from each other, each of the second semiconductor patterns protruding from the substrate; second conductive patterns surrounding the second semiconductor patterns, respectively; and first contact plugs connected to the second conductive patterns, wherein the first structure is a vfet, and the second structure in

Abstract: A semiconductor device includes a semiconductor layer having first and second surfaces, a first electrode and a first gate electrode along the first surface, and a second electrode and a second gate electrode along the second surface. The layer includes a first type first region, a second type second region between the first region and the first surface and facing the first gate electrode, a first type third region between the second region and the first surface and contacting the first electrode, a second type fourth region between the first region and the second surface, facing the second gate electrode, and contacting the second electrode, and a first type fifth region between the fourth region and the second surface and contacting the second electrode. Transistors including the first and second gate electrodes have different threshold voltages that are both positive or negative.

Abstract: A gate structure of a field effect transistor includes a first gate dielectric layer, a second gate dielectric layer, and one or more conductive layers disposed over the first gate dielectric layer and the second gate dielectric layer. The first gate dielectric layer is separated from the second gate dielectric layer by a gap filled with a diffusion blocking layer.

Abstract: A microLED display includes a first main substrate, microLEDs disposed above the first main substrate, a first light blocking layer disposed above the first main substrate to define emission areas, a light guiding layer disposed in the emission areas, and a plurality of connecting structures disposed in the emission areas respectively and electrically connected with the microLEDs.

Abstract: A semiconductor device includes a substrate, an isolation structure, a first gate structure, a second gate structure, a first slot contact structure, a first gate contact structure, and a second gate contact structure. The substrate includes a first active region and a second active region elongated in a first direction respectively. The first gate structure, the second gate structure, and the first slot contact structure are continuously elongated in a second direction respectively. The first gate contact structure and the second gate contact structure are disposed at two opposite sides of the first slot contact structure in the first direction respectively.