Patents Examined by Daniel Rojas
  • System for reducing noise in a chemical sensor array
    Patent number: 8552771
    Abstract: A method including receiving an output signal from a sensor array, providing power to the sensor array and to the first analog-to-digital converter, generating a plurality of clock signals that are synchronous with a primary clock signal, providing a first clock signal of the plurality to the first analog-to-digital converter and providing a second clock signal of the plurality to the first switcher. The first clock signal is asynchronous with the second clock signal.
    Type: Grant
    Filed: April 22, 2013
    Date of Patent: October 8, 2013
    Assignee: Life Technologies Corporation
    Inventors: Jeremy Jordan, Todd Rearick
  • Method of controlling connection establishment in a wireless network
    Patent number: 8554132
    Abstract: A method of controlling connection establishment to transmit or receive audio/video (A/V) data in a wireless network is provided. The method of controlling connection establishment to transmit or receive A/V data in a first device of a wireless network that includes a coordinator and at least one device includes transmitting connection request information required to request connection establishment with a second device and a connection request message which includes capability information of the first device to the second device and receiving a connection response message from the second device in response to the connection request message.
    Type: Grant
    Filed: April 29, 2013
    Date of Patent: October 8, 2013
    Assignee: LG Electronics Inc.
    Inventors: Hyeon Cheol Cho, Beom Jin Jeon, Taek Soo Kim
  • Semiconductor device and system
    Patent number: 8542041
    Abstract: A first transistor has one end and a gate coupled to a first power supply line and other end coupled to a first node. A second transistor has a gate coupled to a second node, one end coupled to the first node, and other end coupled to a third node. A third transistor has one end coupled to a second power supply line, a gate coupled to a fourth node, and other end coupled to the third node. A first bias voltage generation circuit supplies a first bias voltage to the second node. A second bias voltage generation circuit supplies a second bias voltage to the fourth node. Accordingly, the power supply voltage at which the third node is changed from a certain level to another level is set high, and an internal node in a semiconductor device is securely initialized when the power supply voltage is decreased.
    Type: Grant
    Filed: April 6, 2010
    Date of Patent: September 24, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Mitsuhiro Ogai, Hirokazu Yamazaki, Keizo Morita, Kazuaki Yamane, Yasuhiro Fujii, Kazuaki Takai, Shoichiro Kawashima
  • High voltage switch with adjustable current
    Patent number: 8536929
    Abstract: The present disclosure relates to a high voltage switch which may comprise a chain of MOS field-effect transistors (MOSFETs). The current of the individual MOSFETS, and hence the chain, can be controlled by means of adding a current measuring resistance into the source path of the transistors and transmitting the voltage arising there via a capacitor to a gate connector of the transistors.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: September 17, 2013
    Assignee: Bergmann Messgeräte Entwicklung KG
    Inventor: Thorald Horst Bergmann
  • Voltage detector
    Patent number: 8531215
    Abstract: A voltage detector includes a first input terminal, a second input terminal, a first voltage detection circuit, a second voltage detection circuit, and a logic holder circuit. The first input terminal receives a first input voltage. The second input terminal receives a second input voltage. The first voltage detection circuit outputs a first detection signal that switches a logic state thereof when the first input voltage falls below a first detection voltage. The second voltage detection circuit outputs a second detection signal that switches a logic state thereof when the second input voltage falls below a second detection voltage. The logic holder circuit retains the logic state of the first detection signal when the second detection signal indicates that the second input voltage is below the second detection voltage.
    Type: Grant
    Filed: November 10, 2010
    Date of Patent: September 10, 2013
    Assignee: Ricoh Company, Ltd.
    Inventor: Koichi Morino
  • Power management unit for configurable receiver and transmitter and methods for use therewith
    Patent number: 8526893
    Abstract: A configurable transceiver includes an RF receiver that generates a stream of inbound data from at least one received RF signal, wherein the RF receiver is configurable in response to a control signal. An RF transmitter generates at least one RF signal from a stream of outbound data, wherein the RF transmitter section is configurable in response to the control signal. A configuration controller generates the control signal based on channel data. A power management unit generates at least one receiver supply signal and at least on transmitter supply signal in accordance with a plurality of power consumption parameters, and wherein the power management unit adjusts at least one of the plurality of power consumption parameters based on the control signal.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: September 3, 2013
    Assignee: Broadcom Corporation
    Inventor: Ahmadreza Rofougaran
  • Adaptor circuit for power supply
    Patent number: 8513988
    Abstract: A adaptor circuit for a power supply includes a first comparison circuit, a timing circuit; and a second comparison circuit. An input of the first comparison circuit is electrically connected to a PS_ON terminal. The first comparison circuit includes a diode. An input of the second comparison circuit is electrically connected to the diode of the first comparison circuit via the timing circuit. When the PS_ON signal is powered on, the diode is off, and the timing circuit charges up in a predetermined time, and the second comparison circuit outputs a PWR_GOOD signal after the predetermined time. When the PS_ON signal is powered off, the diode turns on, and the timing circuit discharges, so the second comparison circuit stops outputting a PWR_GOOD signal.
    Type: Grant
    Filed: June 19, 2011
    Date of Patent: August 20, 2013
    Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.
    Inventor: Hai-Qing Zhou
  • Delay-locked loop having a loop bandwidth dependency on phase error
    Patent number: 8513991
    Abstract: Circuits, methods, and apparatus that vary one or more attributes or parameters of a closed-loop clock circuit as a function of a characteristic of its phase error. One example provides a delay-locked loop having a loop bandwidth that can be varied as a function of its phase error. In this specific example, current phase error is determined. This determination may be made directly, either by measuring phase error, or indirectly, by determining if phase error is within one or more ranges of values. Once the phase error is determined, the loop bandwidth can be set. In one example, the loop bandwidth is set by adjusting the depth, type, or depth and type of the delay-locked loop's loop filter. In this way, large phase errors can be reduced quickly by increasing loop bandwidth, while small phase errors can be used to decrease loop bandwidth, thereby improving jitter performance.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: August 20, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Youn-Cheul Kim
  • Testing of automobile mounted antennas
    Patent number: 8515358
    Abstract: A method and device provides for the testing and validation of a control module for receiving wireless data and communications utilizes a transmission line coupler mounted proximate the control module generates a signal that couples to an antenna of the control module. The control module produces a signal in response to coupling of the antenna with the signal produced by the transmission line coupler. The resulting signal is utilized to check, verify and validate operation of the control module.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: August 20, 2013
    Assignee: Continental Automotive Systems, Inc.
    Inventors: Matthew Doyle, Jose Rodrigo Camacho-Perez
  • DLL circuit and semiconductor device having the DLL circuit
    Patent number: 8513993
    Abstract: To include a phase-difference-amount detecting circuit that detects an amount of phase difference between an external clock signal and a replica clock signal, a variable delay circuit that delays the external clock signal based on the amount of phase difference to generate an internal clock signal, and a replica buffer that delays the internal clock signal to generate the replica clock signal. According to the present invention, the variable delay circuit is controlled based on the amount of phase difference, instead of being controlled based on whether the phase of the replica clock signal is advanced or delayed with respect to the external clock signal. Accordingly, even when the amount of phase difference is large, a DLL circuit can be locked at a high speed.
    Type: Grant
    Filed: June 16, 2010
    Date of Patent: August 20, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Hiroki Takahashi
  • Data output circuit and data output method thereof
    Patent number: 8508272
    Abstract: A data output circuit and a data output method thereof are provided. The data output circuit includes a delay locked loop, a duty ratio correction block, and an output unit. The delay locked loop corrects a duty ratio of a first internal clock. The delay locked loop includes a correction enable signal output unit configured to output a correction enable signal when the operation of correcting the duty ratio of the first internal clock is completed. The duty ratio correction block corrects the duty ratio of the first internal clock by using a duty ratio detection signal in response to the correction enable signal, and outputs the corrected first internal clock as an output clock. The output unit detects a duty ratio of the output clock, generates the duty ratio detection signal to the duty ratio correction block, and outputs a data strobe signal in response to the output clock.
    Type: Grant
    Filed: May 12, 2010
    Date of Patent: August 13, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jin-Il Chung
  • Receiver circuit with high input voltage protection
    Patent number: 8502568
    Abstract: An integrated circuit 2 includes a receiver circuit 4 for receiving an input signal PAD and converting this to an output signal OUT. Conduction path circuitry 14 couples an input 10 to a first node 16. Buffer circuitry 18 is coupled between the first node 16 and an output 12 carrying the output signal Out. The conduction path circuitry comprises a first PMOS transistor 24 and a second PMOS transistor 26 connected between the input 10 and the first node 16. A first NMOS transistor 28 is connected between the input 10 and the first node 16. The gate of the second PMOS transistor 26 is coupled to the output 12 to directly receive the output signal and thereby achieve rapid cut off of the charging of the node 16 when the input voltage rises beyond a certain level which switches the buffer circuitry 18.
    Type: Grant
    Filed: August 17, 2010
    Date of Patent: August 6, 2013
    Assignee: ARM Limited
    Inventors: Sandeep Dwivedi, Nidhir Kumar, Sridhar Cheruku
  • Apparatus and method for protecting a semiconductor junction
    Patent number: 8502567
    Abstract: Apparatus and methods are disclosed, such as those involving protection of a semiconductor junction of a semiconductor device. One such apparatus includes a bipolar transistor including an emitter, a base, and a collector; a first junction protection device including a first end electrically coupled to the emitter of the bipolar transistor, and a second end electrically coupled to a node; and a second junction protection device including a first end electrically coupled to a voltage reference, and a second electrically coupled to the emitter of the bipolar transistor. Each of the first and second junction protection devices may have a substantially higher leakage current than the leakage current of the base-emitter junction of the bipolar transistor when reverse biased.
    Type: Grant
    Filed: May 25, 2010
    Date of Patent: August 6, 2013
    Assignee: Analog Devices, Inc.
    Inventor: Kenneth Lawas
  • Clock supply apparatus
    Patent number: 8487672
    Abstract: A clock supply apparatus for supplying clock signals to a plurality of circuit blocks includes a supply unit configured to supply, to reset the plurality of circuit blocks, a clock signal rising at timing different from one circuit block to another to each of the plurality of circuit blocks.
    Type: Grant
    Filed: May 23, 2011
    Date of Patent: July 16, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventor: Naotsugu Itoh
  • High voltage input receiver with hysteresis using low voltage transistors
    Patent number: 8482329
    Abstract: A high voltage input receiver with hysteresis using low voltage transistors is disclosed. In one embodiment, an input receiver circuit includes a hysteresis comparator circuit, based on a plurality of low voltage transistors, for generating a first output voltage by comparing an external voltage and a reference voltage and a stress protection circuit for preventing the plurality of low voltage transistors of the hysteresis comparator circuit from exceeding their reliability limits. In addition, the reference voltage is used to set a positive trip point and a negative trip point. Moreover, the input receiver circuit includes a source follower circuit for transferring the first output voltage to an output node of the source follower circuit from a voltage level of a VDDIO to a voltage level of a VDD.
    Type: Grant
    Filed: August 8, 2008
    Date of Patent: July 9, 2013
    Assignee: LSI Corporation
    Inventors: Vani Deshpande, Anuroop Iyengar, Pramod Elamannu Parameswaran, Pankaj Kumar
  • Temperature sensing circuit and method
    Patent number: 8482330
    Abstract: A low cost, low power and low noise temperature sensor circuit is disclosed. A control circuit asserts a start signal and a stop signal, causes a pulse generating circuit to generate a finite number of pulses, whose pulse frequency varies with temperature. A counter counts the finite number of pulses and outputs the count which can be used to represents the temperature. Further, the pulse generating circuit includes a delay circuit, a pulse width controlling circuit, and a synchronizer with asynchronous clear.
    Type: Grant
    Filed: October 7, 2009
    Date of Patent: July 9, 2013
    Assignee: Accusilicon Inc.
    Inventor: Yi Zhou
  • Circuit for controlling PSON signal
    Patent number: 8482324
    Abstract: A circuit includes an ATX power connector with a PSON pin, a time delay circuit, and a stabilizer circuit. The time delay circuit receives an input PSON# signal and then sends an output PSON# signal to the PSON pin of the power connector after a time delay has elapsed. The stabilizer circuit is coupled to the PSON pin of the power connector for stabilizing the output PSON# signal.
    Type: Grant
    Filed: August 7, 2009
    Date of Patent: July 9, 2013
    Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.
    Inventor: Qi-Jie Chen
  • Reset circuit
    Patent number: 8476944
    Abstract: A reset circuit includes two voltage dividing circuits, a switching circuit, a selection button, two voltage converters, and a processor. The voltage converters convert a first or second power supply for supplying power to the processor. When the first power supply supplies power to the processor the processor operates normally. When the second power supply supplies power to the processor, one of the voltage dividing circuits outputs a signal to the processor to restore an electronic device to factory settings according to the signal.
    Type: Grant
    Filed: November 25, 2010
    Date of Patent: July 2, 2013
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventor: Ming-Chih Hsieh
  • Duty cycle correction in a delay-locked loop
    Patent number: 8471617
    Abstract: Circuits, methods, and apparatus that provide duty-cycle error correction for clock and other periodic signals. One example provides a duty-cycle correction that can be used to improve the duty cycle of a clock signal that is received by, or generated by, a delay-locked loop. This example receives an input clock signal and uses a variable delay element to construct an improved duty-cycle output clock signal. The duty cycle of the output clock is examined to determine if the delay element is providing excess or insufficient delay. The delay of the delay element is then adjusted. To improve response times, a successive approximation technique is used to determine the most significant bits of a count that adjusts the delay through the delay element. To improve accuracy, a linear technique is used to adjust the least significant bits of the count.
    Type: Grant
    Filed: June 17, 2010
    Date of Patent: June 25, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Minseok Choi
  • Apparatus with RF transceiver and wireless communication module
    Patent number: 8472891
    Abstract: An apparatus includes an RFID transceiver, a processing module, and a wireless communication module. The RFID transceiver receives an RFID signal from a device and obtains communication information from the RFID signal. The processing module is operable to: determine a wireless communication protocol and device information from the communication information; receive an outbound data request; and generate outbound data in accordance with the outbound data request, wherein the outbound data includes at least a portion of the information. The wireless communication module converts outbound data into an outbound wireless signal in accordance with the wireless communication protocol.
    Type: Grant
    Filed: August 20, 2012
    Date of Patent: June 25, 2013
    Assignee: Broadcom Corporation
    Inventor: Ahmadreza (Reza) Rofougaran