Abstract: Provided is a frequency synthesizer capable of fine setting over a wide band and having a wide frequency pull-in range. A sine wave signal of an output frequency of a voltage controlled oscillating part is quadrature-detected, and in a PLL utilizing a vector rotating at a frequency (velocity) equal to a difference from a frequency of a frequency signal used for the detection, a frequency pull-in means integrates a first constant for increasing the output frequency as a pull-in voltage when a control voltage from the PLL to the voltage controlled oscillating part is larger than a prescribed set range, and integrates a second constant for decreasing the output frequency as the pull-in voltage when the control voltage is smaller than the set range. Then, an adding means adds the control voltage from the PLL and the pull-in voltage from the frequency pull-in means to output an addition result to the voltage controlled oscillating part.

Abstract: A frequency generator is used for generating a frequency within a frequency range. The frequency generator includes a variable current source, a voltage drop generation unit, a voltage source, a detection unit, a conversion unit, and an oscillating circuit. The variable current source is used for outputting a current according to a control signal. The voltage drop generation unit is used for generating a voltage drop according to the current. The voltage source is used for outputting a voltage range. The detection unit is used for outputting the control signal to the variable current source according to a relationship between the voltage drop and the voltage range. The conversion unit is used for outputting a digital code according to the relationship between the voltage drop and the voltage range. The oscillator circuit is used for generating the frequency according to the digital code.

Abstract: A method and system of voltage compensated integrated circuits. Operating characteristics of integrated circuitry are enhanced by application of voltage compensation.

Abstract: The input buffer circuit of a semiconductor apparatus includes a first buffering unit that that is activated by a voltage level difference between a first voltage terminal and a second voltage terminal, and generates a first compare signal and a second compare signal by comparing the voltage levels of reference voltage and an input signal; a control unit that controls the amount of current flowing between the second voltage terminal and a ground terminal by comparing the voltage levels of the reference voltage and the second compare signal; and a second buffering unit that generates an output signal by comparing the voltage levels of the input signal and the first compare signal.

Abstract: A slew rate control circuit is provided. The slew rate control circuit includes at least one switch and an inverter. A first end of the switch is coupled to a power terminal. A toggle end of the switch is coupled to a first control terminal. A second end of the switch is coupled to an output terminal. An output end of the inverter is coupled to the output terminal. An input end of the inverter is coupled to an input terminal. A voltage at the first control terminal conducts the switch to reduce the slew rate when a large voltage variation occurs at the output terminal. A method of controlling a slew rate and a slew rate control device are provided.

Abstract: A method of controlling connection establishment to transmit or receive A/V data in a wireless network is provided. The method of controlling connection establishment to transmit or receive A/V data in a first device of a wireless network that includes a coordinator and at least one device comprises transmitting connection request information required to request connection establishment with a second device and a connection request message which includes capability information of the first device to the second device and receiving a connection response message from the second device in response to the connection request message.

Abstract: An output device includes a main driver that outputs an output signal in accordance with an input signal input thereto, a noise driver that outputs a noise signal containing a noise waveform, a combiner that outputs a combined signal obtained by combining together the output signal and the noise signal, and a controller. The noise driver (i) sets an output end thereof at high impedance when not supplied with an enable signal, and (ii) varies an voltage level of the noise signal to be output therefrom in accordance with how a control signal supplied thereto varies when supplied with the enable signal. The controller controls the noise driver to output the noise signal containing the noise waveform that occurs when the output signal travels through a predetermined transmission line, by controlling a timing at which the control signal varies and a timing at which the enable signal is switched.

Abstract: A method for operating a mobile terminal, and which includes performing voice recognition on call content to produce recognized call content, converting the recognized call content into one or more units of character information, registering the one or more units of character information to one or more particular functions of the mobile terminal based on a type of the character information or a field of the character information, inputting a search parameter, searching one of a plurality of file types and identifying a file related to both the search parameter and the one or more registered units of character information, and displaying or automatically executing the identified file.

Abstract: A method of providing a user interface on a mobile device for enabling a user to select acoustic equalizer settings for voice call downlink audio signals, the mobile device including an internal microprocessor, a display in communication with the microprocessor, and at least one input means in communication with the microprocessor, the method including receiving a request from the user for displaying the user interface, in response to the request, displaying the user interface on the display, the user interface including a plurality of predetermined acoustic equalizer settings, wherein the user selects one of the equalizer settings using the input means, receiving the selected equalizer setting at the microprocessor, storing the selected equalizer setting at the microprocessor, and processing the voice call downlink audio signals according to the selected equalizer setting.

Abstract: The present disclosure relates to on-chip self calibrating delay monitoring circuitry.

Abstract: A frequency synthesizer in which a satisfactory frequency stability can be obtained over the entire long period of service immediately after power activation is disclosed. The reference signal generation circuit includes an OCXO, a TCXO, weight converters which regulate weights with respect to outputs, and an adder which adds up the outputs from the weight converters to output the added output as a reference signal. The CPU controls weight converters B and C so that the weight of the TCXO is set to 100% and the weight of the OCXO is set to 0% at the time of the power activation, so that the weight of the OCXO gradually rises, and so that the weight of the TCXO is set to 0% and the weight of the OCXO is set to 100% after preset time, whereby the frequency can quickly be stabilized after the power activation.

Abstract: An output buffer includes a first output transistor, a first switch, a second switch and a third switch. The first output transistor is connected to a first operational voltage for outputting the first operational voltage as the data signal. The first switch is connected to a bulk of the first output transistor for receiving an enable signal. The second switch is connected to the first switch and a second operational voltage for receiving the enable signal, wherein the second operational voltage is lower than the first operational voltage. The third switch includes a first terminal connected to the bulk of the first output transistor, a control terminal connected to the first switch, and a second terminal connected to the first operational voltage.

Abstract: A power-on reset circuit includes a clamping signal generator and a determining device. The clamping signal generator is adapted to receive a trigger signal, and generates a clamping signal with reference to the trigger signal. The clamping signal generator includes an output unit for generating the clamping signal according to a feedback signal, and a feedback unit for generating the feedback signal according to first and second intermediate signals. The first intermediate signal is generated with reference to the clamping signal. The second intermediate signal is generated according to the trigger signal. The determining device is adapted to receive the trigger signal, is coupled to the clamping signal generator for receiving the clamping signal therefrom, and is operable to generate a reset signal according to the trigger signal and the clamping signal.

Abstract: An input interface circuit according to the present invention includes an input first stage circuit that is connected to a signal terminal, where the signal terminal receives external data, and a phase adjustment circuit that adjusts an external input clock and a latch timing signal to be in phase, where the latch timing signal is output to latch circuits included in the input first stage circuit. The phase adjustment circuit adjusts delay time of the latch timing signal that passes through the clock tree circuit and is supplied to the latch circuit in response to a comparison result between the clock and an output from a replica delay circuit which is replicated from the clock.

Abstract: A peripheral device and a method for programming the read/writeable memory of the RFID circuitry by communications between either RF antenna or bus communications port controller interface or both. In the peripheral device, an EEPROM, bus communications controller interface, NFC interface, antenna, and logic controller operate to receive and transmit configuration and calibration data between a BLUETOOTH circuit and an external BLUETOOTH enabled device. The dual interfaced EEPROM is operable to share or partition its EEPROM between an NFC interface and a bus communications controller.

Abstract: A load driving device includes a power supply terminal, a ground terminal, an output terminal coupled to a load, an output transistor coupled between the power supply and output terminals, a driver circuit supplying a first control signal to turn on the output transistor and a second control signal to turn off the output transistor, a discharge circuit coupled between the control terminal of the output transistor and the output terminal, a compensation circuit that turns on when a potential of the ground terminal is at least a predetermined value to maintain a non-conductive state of the output transistor when a polarity of a power supply coupled between the power supply and ground terminals is normal, and a reverse connection protection circuit coupled between the control terminal and the ground terminal, which brings the output transistor into a conductive state when a polarity of the power supply is reversed.

Abstract: A disclosed semiconductor device includes an input terminal, a power line, a pnp-bipolar transistor connected to the power line, a first resistor connecting an emitter of the transistor to the input terminal, a second resistor connecting a collector of the transistor to ground, an operation circuit operable when the input voltage is a predetermined voltage or higher, the predetermined voltage being set within a first voltage region in which the input voltage cannot turn on the transistor, a comparator comparing an internal voltage with a reference voltage, the internal voltage being changed from a voltage value in a non-conductive state in which the transistor is not turned on, and an output terminal configured to output an output voltage which changes in response to a result of comparing the internal voltage with the reference voltage.

Abstract: Phase interpolator and a delay circuit for the phase interpolator. The phase interpolator includes a variable delay circuit to rotate phase of an input clock to generate a phase rotated signal. The phase interpolator also includes a delay locked loop coupled to the variable delay circuit to generate a plurality of phase shifted outputs. The delay locked loop includes a plurality of delay elements. Each delay element includes a multiplexer and a delay cell coupled to the multiplexer. The multiplexer is configurable using a first control signal to output one of the phase rotated signal and a phase shifted output of the plurality of phase shifted outputs. The delay cell delays one of the phase rotated signal and the phase shifted output to generate another phase shifted output of the plurality of phase shifted outputs.

Abstract: A delay locked loop includes a delay pulse generation unit, a coding unit, and a delay line. The delay pulse generation unit is configured to generate a delay pulse having a certain width. The coding unit is configured to code the delay pulse and output a code value. The delay line is configured to delay an input clock by the code value, and generate a delayed locked clock. The delay pulse has a logic high level state during a third period equivalent to a difference between a first period, which corresponds to an integer multiple of the input clock, and a second period, which is a certain replica delay period.

Abstract: A non-linear effect of a rectifier element is enhanced, an input amplitude is increased by further taking advantage of a resonance circuit, and a rectification efficiency of a rectifier circuit for detection is improved, so that the gain of an amplifier circuit at a latter stage can be set low. RF input terminals 101, 102 are applied with signals at phases opposite to each other. A signal at terminal 102 is applied to a gate of transistor M1 through capacitor C3, and a signal at terminal 101 is applied to node N1 connected with a source of transistor M1 and a gate and a drain of transistor M2 through capacitor C1. 301, 302 designate terminals applied with DC biases, and L1, C15 and L2, C16 are series resonance circuits. Half-wave double voltage rectifier circuits comprised of M1, M2, C1-C3, R1 are connected in cascade at a plurality of stages.