Abstract: To increase the speed with which a Second Layer Address Table (SLAT) is traversed, memory having the same access permissions is contiguously arranged such that one or more hierarchical levels of the SLAT need not be referenced, thereby resulting in more efficient SLAT traversal. “Slabs” of memory are established whose memory range is sufficiently large that reference to a hierarchically lower level table can be skipped and a hierarchically higher level table's entries can directly identify relevant memory addresses. Such slabs are aligned to avoid smaller intermediate memory ranges. The loading of code or data into memory is performed based on a next available memory location within a slab having equivalent access permissions, or, if such a slab is not available, or if an existing slab does not have a sufficient quantity of available memory remaining, a new slab with the proper access permissions is established.

Abstract: A device is configured to receive, from a controller, an instruction requesting data for the device and determine a comparison result value based on a comparison of the data for the device and a reference value. The device is further configured to determine whether to respond to the instruction based on the comparison result value and, in response to a determination to respond to the instruction, output, to the controller, the comparison result value, wherein, to output the comparison result value, the device is configured to refrain from outputting the data for the device.

Abstract: An AI accelerator apparatus using in-memory compute chiplet devices. The apparatus includes one or more chiplets, each of which includes a plurality of tiles. Each tile includes a plurality of slices, a central processing unit (CPU), and a hardware dispatch device. Each slice can include a digital in-memory compute (DIMC) device configured to perform high throughput computations. In particular, the DIMC device can be configured to accelerate the computations of attention functions for transformer-based models (a.k.a. transformers) applied to machine learning applications. A single input multiple data (SIMD) device configured to further process the DIMC output and compute softmax functions for the attention functions. The chiplet can also include die-to-die (D2D) interconnects, a peripheral component interconnect express (PCIe) bus, a dynamic random access memory (DRAM) interface, and a global CPU interface to facilitate communication between the chiplets, memory and a server or host system.

Abstract: A self-detection mechanism for an IC is disclosed that determines whether the IC's internal bus is in a hanging state. An initialization sequence can be modified after a soft reset by reading data from an internal DRAM of the IC using a Direct Memory Access (DMA) controller as part of the initialization sequence. The read command is issued over the internal bus and, if the bus is hanging, the read command is not completed. Monitoring can be performed by waiting a predetermined period of time (e.g., 100 ms) to determine if the read was properly completed. If so, no further action is needed. If the read was not completed, then a hard reset is requested to be performed. Thus, an initialization sequence can be modified to run dummy transactions through the internal bus, and validate that all paths are functional.

Abstract: An integrated circuit includes: a local memory; and a first processing circuit coupled to the local memory. The first processing component is configured to: receive a first set of image data; perform a first image processing operation on the first set of image data to produce a second set of image data; and store at least some of the second set of image data into the local memory. The integrated circuit also includes a second processing circuit coupled to the local memory and configured to: receive at least some of the second set of image data from the local memory; and perform a second image processing operation on the second set of image data to produce a third set of image data.

Abstract: Provided is a verification system and a verification method for an Ethernet interface chip. The verification system comprises a Reconciliation Sublayer (RS), a Physical Coding Sublayer (PCS), a Physical Medium Attachment (PMA) layer, and a flow control unit connecting the RS and the PMA layer, wherein the PMA layer is provided with a PMA clock and a buffer, the buffer is configured to store data transferred from the PCS, and the PMA clock is configured to control the PMA layer to send the data in the buffer to an Ethernet interface chip to be tested.

Abstract: A NVMe™ or NVMe-over-fabrics enabled device with video codec functionality may be seen to overcome scalability problem of known hardware assisted video codec solutions. The device of aspects of the present application may or may not have storage media. A host computer communicates with the device through NVMe™ commands. The device may be in one of many SSD form factors, such as U.2 or AIC. The device may be provided as a component in NVMe-enabled computers or NVMe-over-fabrics-enabled systems.

Abstract: The present application relates to a network-on-chip data processing method. The method is applied to a network-on-chip processing system, the network-on-chip processing system is used for executing machine learning calculation, and the network-on-chip processing system comprises a storage device and a calculation device. The method comprises: accessing the storage device in the network-on-chip processing system by means of a first calculation device in the network-on-chip processing system and obtaining first operation data; performing an operation on the first operation data by means of the first calculation device to obtain a first operation result; and sending the first operation result to a second calculation device in the network-on-chip processing system. According to the method, operation overhead can be reduced and data read/write efficiency can be improved.

Abstract: A reconfigurable compute fabric can include multiple nodes, and each node can include multiple tiles with respective processing and storage elements. Compute kernels can be parsed into directed graphs and mapped to particular node or tile resources for execution. In an example, a branch-and-bound search algorithm can be used to perform the mapping. The algorithm can use a cost function to evaluate the resources based on capability, occupancy, or power consumption of the various node or tile resources.

Abstract: An operating method of a controller that controls a memory device includes initializing a clock frequency set corresponding to clock signals provided to a plurality of operation modules included in the controller when a change in a current performance or a change in a host request pattern is detected, determining a target performance on the basis of the current performance given after the clock frequency set is initialized, determining an optimal clock frequency set, in which the current performance is able to be maintained equal to or greater than the target performance, by repeatedly performing an operation of changing at least one clock frequency included in the clock frequency set and an operation of monitoring the current performance given after the clock frequency is changed, and providing the plurality of operation modules with clock signals according to the optimal clock frequency set.

Abstract: Aspects disclosed herein relate to a method comprising: obtaining a list of data paths to at least one persistent storage device through a plurality of NUMA nodes; associating with each data path, access performance information; receiving a request to access one of the at least one persistent storage device; calculating a preferred data path to the one of the at least one persistent storage device using the access performance information; and accessing the one of the at least one persistent storage device using the preferred data path.

Abstract: An AI accelerator apparatus using in-memory compute chiplet devices. The apparatus includes one or more chiplets, each of which includes a plurality of tiles. Each tile includes a plurality of slices, a central processing unit (CPU), and a hardware dispatch device. Each slice can include a digital in-memory compute (DIMC) device configured to perform high throughput computations. In particular, the DIMC device can be configured to accelerate the computations of attention functions for transformer-based models (a.k.a. transformers) applied to machine learning applications. A single input multiple data (SIMD) device configured to further process the DIMC output and compute softmax functions for the attention functions. The chiplet can also include die-to-die (D2D) interconnects, a peripheral component interconnect express (PCIe) bus, a dynamic random access memory (DRAM) interface, and a global CPU interface to facilitate communication between the chiplets, memory and a server or host system.

Abstract: A drive and control system for a lawn tractor includes a CAN-Bus network, a plurality of controllers, a pair of electric transaxles controlled by the plurality of controllers, and one or more steering and drive input devices coupled to respective sensor(s) for sensing user steering and drive inputs. The plurality of controllers communicate with one or more vehicle sensors via the CAN-Bus network. The plurality of controllers receive the user's steering and drive inputs and posts on the CAN-Bus network and generate drive signals to obtain the desired speed and direction of motion of the lawn tractor.

Abstract: A processing-in-memory (PIM) device includes a plurality of multiplication/accumulation (MAC) units, each of the MAC units including a memory bank and a MAC operator and performing one operation, among a memory operation and a PIM operation, a command mapping register generating one of a memory operation mode signal and a PIM operation mode signal based on a row address that is mapped to the PIM operation to be performed by the plurality of MAC units, and a command decoder generating a memory control signal for the memory operation and a PIM control signal for the PIM operation, wherein the command decoder is configured to generate the PIM control signal in response to the PIM operation mode signal and configured to transmit the PIM control signal to the plurality of MAC units, and configured to generate the memory control signal in response to the memory operation mode signal and configured to transmit the memory control signal to the plurality of MAC units.

Abstract: A processing-in-memory (PIM) system includes a PIM device and a PIM controller. The PIM device includes a first storage region, a second storage region, and a multiplication/accumulation (MAC) operator configured to receive first data and second data from the first and second storage regions, respectively, to perform a MAC arithmetic operation. The PIM controller controls a memory mode and a MAC mode of the PIM device. The PIM controller is configured to generate and transmit a memory command to the PIM device in the memory mode. In addition, the PIM controller is configured to generate and transmit first to fifth MAC commands to the PIM device in the MAC mode.

Abstract: A processor circuit sends a read request. A clock signal of the processor circuit corresponds to a first counting value. A memory circuit stores data and sends a data strobe signal in response to the read request. The data strobe signal corresponds to a second counting value. The processor circuit includes a selector circuit and a feedback circuit. The selector circuit selects and outputs a flag signal from a plurality of flag control signals according to the second counting value. The feedback circuit generates an enable signal according to a set signal associated with the first counting value, the flag signal associated with the second counting value, and a data strobe gate signal, and generates the data strobe gate signal according to the enable signal and the data strobe signal. The processor circuit reads the data according to the data strobe gate signal.

Abstract: A processing-in-memory (PIM) system includes a PIM device and a PIM controller. The PIM device includes a first storage region, a second storage region, and a multiplication/accumulation (MAC) operator configured to receive first data and second data from the first and second storage regions, respectively, to perform a MAC arithmetic operation. The PIM controller controls a memory mode and a MAC mode of the PIM device. The PIM controller is configured to generate and transmit a memory command to the PIM device in the memory mode. In addition, the PIM controller is configured to generate and transmit first to fifth MAC commands to the PIM device in the MAC mode.

Abstract: One example relates to a device that includes an activity monitor. The activity monitor includes a bus interface having inputs coupled to receive signals from a bus and having outputs coupled to provide signals to an other device. The activity monitor monitors the bus for a message directed to a predefined address that is associated with the other device in response to detecting that the other device is a low power sleep mode, the activity monitor outputs the predefined address to the other device to enable the other device to capture the predefined address, via the bus interface, in response to the monitored address matching the predefined address that is associated with the other device.

Abstract: The present application relates to a network-on-chip data processing method. The method is applied to a network-on-chip processing system, the network-on-chip processing system is used for executing machine learning calculation, and the network-on-chip processing system comprises a storage device and a calculation device. The method comprises: accessing the storage device in the network-on-chip processing system by means of a first calculation device in the network-on-chip processing system, and obtaining first operation data; performing an operation on the first operation data by means of the first calculation device to obtain a first operation result; and sending the first operation result to a second calculation device in the network-on-chip processing system. According to the method, operation overhead can be reduced and data read/write efficiency can be improved.

Abstract: In a method of operating an audio subsystem and a universal serial bus (USB) module, the audio subsystem receives a reference clock signal from the USB module. A USB direct memory access (UDMA) block included in the audio subsystem performs an automatic restart every predetermined period in synchronization with the reference clock signal. The UDMA block transmits data having a predetermined size to the USB module by performing a direct memory access (DMA) operation whenever the automatic restart is performed.