Abstract: A system for monitoring inter-integrated circuit (12C) communication includes a power supply, a battery backup unit, an 12C serial clock line (SCL) coupled between the power supply and the battery backup unit, an 12C serial data line (SDA) coupled between the power supply and the battery backup unit, and a controller. A first monitor line is coupled between the controller and the 12C serial clock line, and a second monitor line is coupled between the controller and the 12C serial data line. The controller is configured to monitor a digital communication transmitted on the 12C serial clock and data lines between the power supply and the battery backup unit, interpret a message included in the monitored digital communication, and perform a control function according to the interpreted message.

Abstract: A device comprising: a bus forming a ring path for circulation of one or more data packets around the bus, wherein the one or more data packets comprises a trace report packet for collecting trace data from a plurality of components attached to the bus, wherein the bus is configured to repeatedly circulate the trace report packet with a fixed time period taken for each circulation of the ring path performed by the trace report packet; and the plurality of components, each of which comprises circuitry configured to, upon reception of the trace report packet at the respective component, insert one or more items of the trace data that have been obtained by the respective component.

Abstract: According to one embodiment, a controller of a memory system writes write data associated with a set of received write requests to a first write destination storage region in a first write mode of writing a plurality of bits per memory cell, without writing the write data to a second storage region. When receiving from a host a first request to cause a state of the first write destination storage region to transition to a second state in which writing is suspended, the controller transfers un-transferred remaining write data from a write buffer of the host to an internal buffer, and writes the remaining write data to the second storage region in a second write mode of writing 1 bit per memory cell.

Abstract: Various embodiments described herein provide for adjusting (e.g., increasing) buffer memory space, provided by memory (e.g., active memory) of a memory sub-system used to store logical-to-physical memory address (L2P) mapping data, by reducing the amount of L2P mapping data stored on the memory.

Abstract: A data processing system includes a memory system including a memory device storing data and a controller performing a data program operation or a data read operation with the memory device, and a host suitable for requesting the data program operation or the data read operation from the memory system. The controller can perform a serial communication to control a memory which is arranged outside the memory system and engaged with the host.

Abstract: Based on power on of an electronic device, a location of first data in a NAND flash memory of an electronic device is determined. The first data is transmitted to a shadow RAM of the electronic device, outputting the first data is output from the shadow RAM to a host device of the electronic device through a serial peripheral interface (SPI) when accessing the location of the first data in the NAND Flash memory.

Abstract: Exemplary aspects for a specific example concern a radar system having sensor circuitry including multiple radar sensors to provide sensor data via multiple virtual channels and multiple data types, a memory circuit with memory buffers, and a bus-interface circuit to control bus interconnects for bus communications involving a radar signal transmitter and the memory circuit. Radar signals are received and processed, via data acquisition path circuitry in multiple circuit paths and via streams of data in response to and to accommodate the operations of the sensor circuitry. A master controller conveys data, via the bus-interface circuit, to the buffers for the sensor data, and generates selectable-type transactions to be linked in selected ones of the buffers, in response to the data provided from the sensor circuitry and based on the sensor data being provided via different ones of the multiple virtual channels and of the multiple data types.

Abstract: A data processing method and system, where the method includes: receiving, by a non-volatile memory express (NVMe) controller, a first Peripheral Component Interconnect express (PCIe) packet sent by a host, where a memory in the NVMe controller is provided with at least one input/output (I/O) submission queue, and the first PCIe packet includes entrance information of a target I/O submission queue and at least one submission queue entry (SQE); and storing the at least one SQE in the target I/O submission queue based on the entrance information of the target I/O submission queue. Therefore, an NVMe data processing process is simplified and less time-consuming, and data processing efficiency is improved.

Abstract: A hybrid electrical and optic system-on-chip (SOC) device configured for both electrical and optic communication includes a substrate, an electrical device configured for electrical communication arranged on the substrate, a photonics device configured for optic communication arranged on the substrate, and a self-test module arranged on the substrate. The self-test module is configured to receive a loop-back signal indicative of an optical signal output from the photonics device and calibrate the photonics device based on the loop-back signal.

Abstract: A method and system for recording and logging errors in a computer system includes reading first error handling information with respect to a transaction. The first error handling information is stored in a first component, and based upon a condition of the storage in the first component, an oldest error information is evicted from the first component.

Abstract: A method includes receiving, by a processing device, an indication that a host system is to become idle for a first period of time, identifying, by the processing device based on the first period of time, a background operation at a memory sub-system, and causing, by the processing device, execution of the background operation at the memory sub-system during the first period of time.

Abstract: An integrated circuit includes a functional core configured to execute functional logic instructions; a functional memory device coupled to the functional core; a safety core configured to execute safety check logic instructions; a monitored address memory device coupled to the functional core and the safety core, the monitored address memory device configured to store memory addresses to be monitored; and a first safety memory device coupled to the functional memory device and the safety core. When a value in one of the monitored memory addresses changes, the changed value of the one of the monitored memory addresses is stored in the functional memory device and in the first safety memory device. The safety core performs a safety check on the changed value of the one of the monitored memory addresses stored in the first safety memory device.

Abstract: Improving performance in solid state devices (SSDs) by controlling or throttling the depth of the request queue. In one implementation, a method includes monitoring a request queue in a solid state device (an SSD), the request queue comprising a first request and a second request having an actual time interval therebetween, determining a number of active memory dies of the SSD, determining a target interval based on the number of active memory dies and a target number of active memory dies, and responsive to the actual time interval being less than the target interval, delaying acting on the second request until after the target interval.

Abstract: A system timer bus used by the processor elements in an ARM-based system on a chip (SoC) is driven using a Precision Time Measurement (PTM) value. This allows the processor elements to be synchronized to the PCIe ports that use PTM. When two SoCs are connected using PCIe links, this example allows the processor elements in both SoCs to be synchronized. As the processor elements are synchronized, associated tasks on the two SoCs are synchronized, so that overall operations are synchronized.

Abstract: Methods, systems, and devices for signal path biasing in an electronic system (e.g., a memory system) are described. In one example, a memory device, a host device, or both may be configured to bias a signal path, between an idle state and an information transfer or between an information transfer and an idle state, to an intermediate or mid-bias voltage level, which may reduce signal interference associated with such transitions. In various examples, the described biasing to a voltage, such as a mid-bias voltage, may be associated with an access command or other command for information to be communicated between devices of the electronic system, such as a command for information to be communicated between a memory device and a host device.

Abstract: A stand-alone bridging test method is provided, which is applied to a stand-alone bridging device. The stand-alone bridging device is coupled to a storage device. The stand-alone bridging device includes a bridging controller. The storage device includes a device controller and a device memory. The stand-alone bridging test method includes the bridging controller generates a handshaking test signal and transmits the handshaking test signal to the device controller. The device controller generates a confirmation test signal according to the handshaking test signal and transmits the confirmation test signal to the bridging controller. The bridging controller generates a test data according to the confirmation test signal and transmits a write command to the device controller to write the test data into the device memory. The bridging controller transmits a read command to the device controller to read a stored data of the device memory.

Abstract: A first logical page type and a second logical page type each comprising a plurality of programming distributions of a memory device are identified. A determination is made that the bit error rate (BER) for the first logical page type is less than a BER for the second logical page type. A set of rules corresponding to a determination that the BER for the first logical page type is less than the BER for the second logical page type is identified. A program targeting rule of the set of rules is determined based on a valley between an erase distribution and a programming distribution adjacent to the erase distribution having a lowest valley margin of a plurality of valley margins corresponding to the plurality of programming distributions of the memory device. Based on the program targeting rule, a program targeting operation is performed to adjust a voltage associated with one or more programming distributions of the memory device.

Abstract: Applying a rate limit across a plurality of storage systems, including: determining a rate limit for paired storage systems; receiving, by a first storage system, an amount of I/O operations serviced by the second storage system during a previous predetermined period of time; determining whether the amount of I/O operations serviced by the second storage system is less than half of the rate limit for the paired storage systems; if so, setting local a rate limit for a next predetermined period of time for the first storage system to the difference between the rate limit for the paired storage systems and the amount of I/O operations serviced by the second storage system during the previous predetermined period of time; and otherwise, setting a local rate limit for a next predetermined period of time for the first storage system to half of the rate limit for the paired storage systems.

Abstract: A chip includes a dedicated scheduler, a general scheduler, and a plurality of hardware accelerators. The hardware accelerators are connected, at least one hardware accelerator is connected to the dedicated scheduler, and at least one hardware accelerator is connected to the general scheduler.

Abstract: A docking station and a control method thereof are provided. The docking station includes a first USB interface, a second USB interface, a video signal output terminal, a microcontroller, a first signal multiplexer, a second signal multiplexer, a video signal processor, and a video signal converter. The microcontroller determines whether the first USB interface or the second USB interface is connected to an electronic device. When the first USB interface is connected to the electronic device, the microcontroller sets the first USB interface as an uplink port. The uplink port receives a signal from the electronic device, and selects and outputs a video signal through the signal. The video signal processor is configured to receive and process the video signal. The video signal converter converts the video signal into a video output signal that is capable of being output to the video signal output terminal for playing.