Abstract: The present application relates to a network-on-chip data processing method. The method is applied to a network-on-chip processing system, the network-on-chip processing system is used for executing machine learning calculation, and the network-on-chip processing system comprises a storage device and a calculation device. The method comprises: accessing the storage device in the network-on-chip processing system by means of a first calculation device in the network-on-chip processing system, and obtaining first operation data; performing an operation on the first operation data by means of the first calculation device to obtain a first operation result; and sending the first operation result to a second calculation device in the network-on-chip processing system. According to the method, operation overhead can be reduced and data read/write efficiency can be improved.

Abstract: In a method of operating an audio subsystem and a universal serial bus (USB) module, the audio subsystem receives a reference clock signal from the USB module. A USB direct memory access (UDMA) block included in the audio subsystem performs an automatic restart every predetermined period in synchronization with the reference clock signal. The UDMA block transmits data having a predetermined size to the USB module by performing a direct memory access (DMA) operation whenever the automatic restart is performed.

Abstract: There is provided a setting device including a setting unit configured to, based on setting content input/output to/from some interfaces among a plurality of interfaces, when the setting content includes setting content related to other interfaces, perform setting for the other interfaces.

Abstract: The present application relates to a network-on-chip data processing method. The method is applied to a network-on-chip processing system, the network-on-chip processing system is used for executing machine learning calculation, and the network-on-chip processing system comprises a storage device and a calculation device. The method comprises: accessing the storage device in the network-on-chip processing system by means of a first calculation device in the network-on-chip processing system and obtaining first operation data; performing an operation on the first operation data by means of the first calculation device to obtain a first operation result; and sending the first operation result to a second calculation device in the network-on-chip processing system. According to the method, operation overhead can be reduced and data read/write efficiency can be improved.

Abstract: A method for data processing of an interconnection protocol, a controller and a storage device, the method comprising in processing of frame sending by a first device to a second device: allocating a plurality of start-of-frame (SOF)-included protocol data units (PDUs) to a designated lane among a plurality of active lanes of the first device; and configuring a PDU distance among the plurality of start-of-frame (SOF)-included protocol data units to be greater than or equal to a product of a maximum bus width of a lane of the interconnection protocol and a quantity of the plurality of active lanes. Accordingly, the method can help greatly reduce the complexity of the hardware protocol engine implemented under the interconnection protocol, especially the complexity of the decoder in the data link layer receiver, thus reducing the difficulty of research and development, verification and maintenance.

Abstract: An endpoint interface device architecture utilized in multi-drop communication networks, such as the RS485 architecture, that utilizes control logic software/firmware within the endpoint microprocessor to isolate shorted lines from the communication transceiver, and to communicate status information to a first or second data source.

Abstract: A memory system of an embodiment is connectable to a host and includes a nonvolatile memory and a memory controller. The memory controller includes: a signal line which transfers a signal sent from the host; a resistance element disposed between and electrically connected to the signal line and a wiring line given a reference potential of the memory system; a switching element connected serially to the resistance element and capable of switching a connection between the signal line and the wiring line; and a control circuit which controls the switching element to switch the connection between the signal line and the wiring line from a connected state to a disconnected state, when a change from a first potential to a second potential occurs on the signal line or when a change from the second potential to the first potential occurs on the signal line.

Abstract: A memory device including memory cells operating according to a first clock signal having a first clock frequency and accessed based on a data access time. The memory device may include a clock shifter circuit for delaying the access commands based on the data access time. The clock shifter circuitry include a shift register circuit and a phase correction circuit. The shift register circuit delays the access commands using a second clock signal having a fraction of the first clock frequency. The phase correction circuit receives the access commands from the shift register circuitry using the fraction of the first clock frequency, delays the access commands based on phase information of the access commands, and outputs the access commands to the memory cells based on the data access time using the first clock frequency.

Abstract: A method of transferring data between a memory controller and at least one memory module via a primary data bus having a primary data bus width is disclosed. The method includes accessing a first one of a memory device group via a corresponding data bus path in response to a threaded memory request from the memory controller. The accessing results in data groups collectively forming a first data thread transferred across a corresponding secondary data bus path. Transfer of the first data thread across the primary data bus width is carried out over a first time interval, while using less than the primary data transfer continuous throughput during that first time interval. During the first time interval, at least one data group from a second data thread is transferred on the primary data bus.

Abstract: A multichip package having a main die coupled to one or more daughter dies is provided. The main die may include embedded universal interface blocks (UIB) each of which can be used to interface with a corresponding daughter die to support high bandwidth parallel or serial communications. Each UIB may include an integrated processor subsystem and associated pattern sequencing logic to perform interface initialization and margining operations. Each UIB may perform simultaneous accesses to a daughter die across one or more channels. Each UIB may also include multiple phase-locked loop circuits for providing different clock signals to different portions of the UIB and a 2× clock phase generation logic. Each UIB may include multiple IO modules, each of which may optionally include its own duty cycle correction circuit. Each IO module may include buffer circuits, each of which may have a de-emphasis control logic for adjusting buffer drive strength.

Abstract: A method for dispatching input-output in a system. The system may include a centralized processing circuit, a plurality of persistent storage targets, a first input-output processor, and a second input-output processor. The method may include determining whether the first input-output processor is connected to a first target of the plurality of persistent storage targets; determining whether the second input-output processor is connected to the first target; and in response to determining that both the first input-output processor is connected to the first target, and the second input-output processor is connected to the first target, dispatching a first plurality of input-output requests, each to either the first input-output processor or the second input-output processor, the dispatching being in proportion to a service rate of the first input-output processor to the first target and a service rate of the second input-output processor to the first target, respectively.

Abstract: Provided is a cable connected between a first electronic device and a second electronic device. A determination unit determines whether or not the first electronic device is a compatible electronic device. A control unit performs control to operate in a compatible mode when the first electronic device is a compatible electronic device and operate in a non-compatible mode when the first electronic device is not a compatible electronic device on the basis of the determination result by the determination unit. Furthermore, an electronic device is connected to an external device via the cable. The determination unit determines whether or not the cable is a compatible cable. The control unit performs control to operate in the compatible mode when the cable is a compatible cable and operate in the non-compatible mode when the cable is not a compatible cable on the basis of the determination result by the determination unit.

Abstract: A secondary processor device ownership system includes a chassis that houses a plurality of devices, a secondary processing system, and a central processing system that includes an integrated switch device that is coupled to each of the plurality of devices and the secondary processing system. The central processing system is configured to provide a device ownership subsystem that configures the central processing system to own a first subset of the plurality of devices, configures the secondary processing system to own a second subset of the plurality of devices, and hides the second subset of the plurality of devices from at least one application provided by the central processing system.

Abstract: Disclosed is a storage device which includes an interface circuit that exchanges data with a host device, and a power management unit that supplies a power to the interface circuit. The interface circuit includes a first input terminal receiving a first signal from the host device, a second input terminal receiving a second signal complementary to the first signal from the host device, a receive module processing the first signal and the second signal, a squelch circuit detecting levels of the first signal and the second signal, and a reference clock detector detecting whether a reference clock for operating the storage device is received. The power management unit selectively supplies a power to the squelch circuit based on a result of the detection by the reference clock detector.

Abstract: An endpoint interface device architecture utilized in multi-drop communication networks, such as the RS485 architecture, that utilizes control logic software/firmware within the endpoint microprocessor to isolate shorted lines from the communication transceiver, and to communicate status information to a first or second data source.

Abstract: A real-time computational device includes a programmable real-time processor, a communications input port which is connected to the programmable real-time processor through a first broadside interface, and a communications output port which is connected to the programmable real-time processor through a second broadside interface. Both broadside interfaces enable 1024 bits of data to be transferred across each of the broadside interfaces in a single clock cycle of the programmable real-time processor.

Abstract: A processing-in-memory (PIM) system includes a plurality of PIM devices, a plurality of PIM controllers configured to control respective ones of the plurality of PIM devices, and an interface coupled between a host and the plurality of PIM controllers. The interface transmits first request data to a target PIM controller corresponding to one of the plurality of PIM controllers for execution of a first request output from the host. The interface transmits second request data to all of the plurality of PIM controllers for execution of a second request output from the host.

Abstract: In some examples, a system aggregates operational metric data of a plurality of storage volumes into aggregated operational metric data groups that correspond to different workload types of workloads for accessing data of a storage system. The system computes an operational metric for a first workload type of the different workload types, the operational metric relating to a resource of the storage system, where the computing of the operational metric for the first workload type comprises inputting aggregated operational metric data of a first aggregated operational metric data group of the aggregated operational metric data groups into a model trained at a system level of the storage system.

Abstract: An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.

Abstract: Systems and methods for processing commands at a random access memory. A series of commands are received to read data from the random access memory or to write data to the random access memory. The random access memory can process commands at a first rate when the series of commands matches a pattern, and at a second, slower, rate when the series of commands does not match the pattern. A determination is made as to whether the series of commands matches the pattern based on at least a current command and a prior command in the series of commands. A ready signal is asserted when said determining determines that the series of commands matches the pattern, where the random access memory is configured to receive and process commands faster than the second rate when the pattern is matched and the ready signal is asserted over a period of multiple commands.