Abstract: One example relates to a device that includes an activity monitor. The activity monitor includes a bus interface having inputs coupled to receive signals from a bus and having outputs coupled to provide signals to an other device. The activity monitor monitors the bus for a message directed to a predefined address that is associated with the other device in response to detecting that the other device is a low power sleep mode, the activity monitor outputs the predefined address to the other device to enable the other device to capture the predefined address, via the bus interface, in response to the monitored address matching the predefined address that is associated with the other device.

Abstract: A self-detection mechanism for an IC is disclosed that determines whether the IC's internal bus is in a hanging state. An initialization sequence can be modified after a soft reset by reading data from an internal DRAM of the IC using a Direct Memory Access (DMA) controller as part of the initialization sequence. The read command is issued over the internal bus and, if the bus is hanging, the read command is not completed. Monitoring can be performed by waiting a predetermined period of time (e.g., 100 ms) to determine if the read was properly completed. If so, no further action is needed. If the read was not completed, then a hard reset is requested to be performed. Thus, an initialization sequence can be modified to run dummy transactions through the internal bus, and validate that all paths are functional.

Abstract: A drive and control system for a lawn tractor includes a CAN-Bus network, a plurality of controllers, a pair of electric transaxles controlled by the plurality of controllers, and one or more steering and drive input devices coupled to respective sensor(s) for sensing user steering and drive inputs. The plurality of controllers communicate with one or more vehicle sensors via the CAN-Bus network. The plurality of controllers receive the user's steering and drive inputs and posts on the CAN-Bus network and generate drive signals to obtain the desired speed and direction of motion of the lawn tractor.

Abstract: In one or more embodiments, one or more systems, one or more methods, and/or one or more processes may determine, via a baseboard management controller (BMC) of an information handling system, to provide firmware to a component of the information handling system; may provide, via the BMC, first data to the component via a first bus; based at least on the first data, may provide, via a communications bridge of the component, a first signal to a non-volatile memory medium (NVMM) of the component, a multiplexer of the component, and an integrated circuit of the component, in which the first signal causes the integrated circuit to be held in a reset state, causes a write protection of the NVMM to be cleared, and causes the multiplexer to couple the BMC to the NVMM; and may provide, via the BMC, the firmware to the NVMM via the multiplexer.

Abstract: A NVMe™ or NVMe-over-fabrics enabled device with video codec functionality may be seen to overcome scalability problem of known hardware assisted video codec solutions. The device of aspects of the present application may or may not have storage media. A host computer communicates with the device through NVMe™ commands. The device may be in one of many SSD form factors, such as U.2 or AIC. The device may be provided as a component in NVMe-enabled computers or NVMe-over-fabrics-enabled systems.

Abstract: In a method of operating an audio subsystem and a universal serial bus (USB) module, the audio subsystem receives a reference clock signal from the USB module. A USB direct memory access (UDMA) block included in the audio subsystem performs an automatic restart every predetermined period in synchronization with the reference clock signal. The UDMA block transmits data having a predetermined size to the USB module by performing a direct memory access (DMA) operation whenever the automatic restart is performed.

Abstract: A drive and control system for a utility vehicle includes a CAN-Bus network and a vehicle control module operable to communicate signals to and from one or more components via the CAN-Bus network. The system includes first and second electric actuators with first and second electronic drive modules, respectively. The system includes a steering and drive input device and a steering and drive sensor module operable to post on the CAN-Bus network a steering and drive input command. The vehicle control module processes the steering and drive input command and post on the CAN-Bus network a steering and drive output command. The first and second electronic drive modules process and convert the steering and drive output command to appropriate first and second actuator commands to drive the first and second electric actuators to obtain the desired speed and direction of motion of the utility vehicle.

Abstract: The cable is connected between a first electronic device and a second electronic device. A determination unit determines whether or not the first electronic device is a compatible electronic device. A control unit performs control to operate in a compatible mode when the first electronic device is a compatible electronic device and operate in a non-compatible mode when the first electronic device is not a compatible electronic device on the basis of the determination result by the determination unit. Furthermore, an electronic device is connected to an external device via the cable. The determination unit determines whether or not the cable is a compatible cable. The control unit performs control to operate in the compatible mode when the cable is a compatible cable and operate in the non-compatible mode when the cable is not a compatible cable on the basis of the determination result by the determination unit.

Abstract: A method of operating a storage controller that communicates with a host including a submission queue and a completion queue is provided. The operating method includes receiving a submission queue doorbell from the host, fetching a first command including a latency from the submission queue of the host in response to the received submission queue doorbell, processing the fetched first command, and writing a first completion, which indicates that the first command is completely processed, into the completion queue of the host at a timing based on the latency.

Abstract: Various embodiments described herein provide for adjusting (e.g., increasing) buffer memory space, provided by memory (e.g., active memory) of a memory sub-system used to store logical-to-physical memory address (L2P) mapping data, by reducing the amount of L2P mapping data stored on the memory.

Abstract: A data processing system includes a controller configured to control data input/output for a memory according to a request of a host. The controller may include a buffer memory including a plurality of buffers configured to store data transmitted from the memory, a processor group including a plurality of cores respectively connected to the plurality of buffers, each core configured to read respective data from its respective buffer and perform computation using the read data, and a speed control component configured to adjust an operating speed of the processor group based on an amount of unread data of each buffer corresponding to each of the plurality of cores.

Abstract: A controller device is disclosed. The controller device comprises a communication interface that is configured to receive a data operation request via an interconnect bus. The controller device comprises an integrated interconnect protocol component that is configured to handle communication via the interconnect bus that supports coherency across a plurality of different processing devices external to the controller device. An integrated memory or storage controller component on the same controller device is configured to handle the data operation request including by being configured to manage communication with a memory or data storage device external to the controller device.

Abstract: A chip system including I/O pins, a memory chip and a processing chip is provided. The processing chip includes I/O pads, memory access pads, a processor, an I/O controller, a memory controller and a transmission gate module. Under an operation mode, the I/O controller allows the processor to communicate with an external circuit device through the I/O controller, the I/O pads and the I/O pins. Under the operation mode, the memory controller allows the processor to access the memory chip through the memory controller and the memory access pads. The transmission gate module is enabled during a program mode or a test mode to allow the external circuit device to perform programming or testing on the memory chip through the I/O pins, the I/O pads, the transmission gate module and the memory access pads.

Abstract: A system includes a data transmission unit, a termination resistor and a data reception unit. The data transmission unit may drive a data transmission line based on data, and drive the data transmission line to a voltage level corresponding to a termination voltage during a specified operation period. The termination resistor may be coupled between the data transmission line and a termination node. The data reception unit may receive a signal transmitted through the data transmission line.

Abstract: A method of transferring data between a memory controller and at least one memory module via a primary data bus having a primary data bus width is disclosed. The method includes accessing a first one of a memory device group via a corresponding data bus path in response to a threaded memory request from the memory controller. The accessing results in data groups collectively forming a first data thread transferred across a corresponding secondary data bus path. Transfer of the first data thread across the primary data bus width is carried out over a first time interval, while using less than the primary data transfer continuous throughput during that first time interval. During the first time interval, at least one data group from a second data thread is transferred on the primary data bus.

Abstract: Improving performance in solid state devices (SSDs) by controlling or throttling the depth of the request queue. In one implementation, a method includes monitoring a request queue in a solid state device (an SSD), the request queue comprising a first request and a second request having an actual time interval therebetween, determining a number of active memory dies of the SSD, determining a target interval based on the number of active memory dies and a target number of active memory dies, and responsive to the actual time interval being less than the target interval, delaying acting on the second request until after the target interval.

Abstract: The present invention includes an integrated system-on-chip device configured on a substrate member. The device has a data input/output interface provided on the substrate member and configured for a predefined data rate and protocol. The device has an input/output block provided on the substrate member and coupled to the data input/output interface. The input/output block comprises a SerDes block, a CDR block, a compensation block, and an equalizer block. The SerDes block is configured to convert a first data stream of N having a first predefined data rate at a first clock rate into a second data stream of M having a second predefined data rate at a second clock rate. The device has a driver module provided on the substrate member and coupled to a signal processing block, and a driver interface provided on the substrate member and coupled to the driver module and a silicon photonics device.

Abstract: An electronic device is provided. The electronic device includes a board, a first latch mechanism, and an expansion card. A controller is disposed on the board. The first latch mechanism is disposed on the board. The first latch mechanism is electrically connected to the controller. The expansion card is plugged in the first latch mechanism and disposed over the board. The expansion card is electrically connected to the controller through the first latch mechanism. The controller determines a connecting condition of the first latch mechanism according to a connecting signal provided by the expansion card.

Abstract: According to one embodiment, a controller of a memory system writes write data associated with a set of received write requests to a first write destination storage region in a first write mode of writing a plurality of bits per memory cell, without writing the write data to a second storage region. When receiving from a host a first request to cause a state of the first write destination storage region to transition to a second state in which writing is suspended, the controller transfers un-transferred remaining write data from a write buffer of the host to an internal buffer, and writes the remaining write data to the second storage region in a second write mode of writing 1 bit per memory cell.

Abstract: Systems and methods for processing commands at a random access memory. A series of commands are received to read data from the random access memory or to write data to the random access memory. The random access memory can process commands at a first rate when the series of commands matches a pattern, and at a second, slower, rate when the series of commands does not match the pattern. A determination is made as to whether the series of commands matches the pattern based on at least a current command and a prior command in the series of commands. A ready signal is asserted when said determining determines that the series of commands matches the pattern, where the random access memory is configured to receive and process commands faster than the second rate when the pattern is matched and the ready signal is asserted over a period of multiple commands.