Abstract: A method of playing a wagering rummy-type card game on an electronic device wherein the object of the game is to create sets or melds of cards that each comprise exactly a straight, flush, straight flush, royal flush, and/or like ranks. The game begins with a total wager from each player, the total comprising at least one separate wager, and is played with a predetermined number of initially-dealt cards to each player. The initially-dealt cards are placed into and completely fill at least two melds. Preferably the cards are automatically placed into the melds by an Optimum Expected Value function. Each player then has the option of folding, or alternately forfeiting one wager or placing an additional wager to receive each of a predetermined number of community cards that are then sequentially dealt. The player has the option to replace any card in any meld with a community card, and the cards in the melds may be rearranged after any replacement.

Abstract: A semiconductor device with improved reliability, in which increase in power consumption can be reduced. The semiconductor device includes an antenna for transmitting and receiving a wireless signal to/from a communication device and at least first and second functional circuits electrically connected to the antenna. The first functional circuit includes a power supply control circuit for controlling power supply voltage output from a power supply circuit in the second functional circuit. A power supply control circuit in the second functional circuit includes a transistor of which first terminal is electrically connected to an output terminal of the power supply circuit and second terminal is electrically connected to a ground line. A gate terminal of the transistor is electrically connected to the power supply control circuit included in one functional circuit.

Abstract: A semiconductor device is made by forming a first active device on a first side of a semiconductor wafer. A first insulating layer is formed over the first side of the wafer. A first conductive layer is formed over the first insulating layer. A first interconnect structure is formed over the first insulating layer and first conductive layer. A temporary carrier is mounted to the first interconnect structure. A second active device is formed on a second side of the semiconductor wafer. A second insulating layer is formed over the second side of the wafer. A second conductive layer is formed over the second insulating layer. A second interconnect structure is formed over the second insulating layer and second conductive layer. The temporary carrier is removed, leaving a double-sided semiconductor device. The double-sided semiconductor device is enclosed in a package with the first and second interconnect structures electrically connected.

Abstract: An integrated circuit package having a die pad with a first face and a second face, a plurality of inner leads, and a plurality of sides between the first face and the second face. The plurality of inner leads is disposed substantially co-planer with and substantially around the die pad. The package also comprises a plurality of outer leads disposed substantially co-planar with and substantially around the plurality of inner leads and the die pad, so that the sides of each of the plurality of outer leads are offset from the sides of each of the plurality of inner leads. A first adhesive layer disposed on the first face of the die pad and a second adhesive layer disposed on the first faces of each of the plurality of inner leads. An IC chip is coupled to the first face of the die pad through the first adhesive layer and to the plurality of inner leads through the second adhesive layer. The package further comprises wires linking the inner leads and outer leads to the IC chip.

Abstract: A system and method for forming post passivation discrete components, is described. High quality discrete components are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer.

Abstract: A method of forming a material on a substrate is disclosed. In one embodiment, the method includes forming a tantalum nitride layer on a substrate disposed in a plasma process chamber by sequentially exposing the substrate to a tantalum precursor and a nitrogen precursor, followed by reducing a nitrogen concentration of the tantalum nitride layer by exposing the substrate to a plasma annealing process. A metal-containing layer is subsequently deposited on the tantalum nitride layer.

Abstract: A leadframe employed by a leadless package comprises a plurality of package units and an adhesive tape. Each of the package units has a die pad with a plurality of openings and a plurality of pins disposed in the plurality of openings. The adhesive tape is adhered to the surfaces of the plurality of package units and fixes the die pad and the plurality of pins.

Abstract: A method of manufacturing a light-emitting device includes, when sealing a light-emitting element on a mounting portion by a glass material softened by heating or when processing the glass material after the sealing, producing a concave portion partially on the glass material by partially contacting and pressing a die against an upper surface of the glass material such that a part of the upper surface being not in contact with the die is deformed and forms a curved surface.

Abstract: A method for assembling semiconductor devices includes providing a first semiconductor device, securing spacers to noncircuit bond pads of the first semiconductor device, and positioning a second semiconductor device on the spacers. Adhesive material may be applied to a surface of one or both of the first and second semiconductor devices prior to positioning of the second semiconductor device, or introduced between first and second semiconductor devices. The noncircuit bond pads may be electrically isolated from other structures of the first semiconductor device or communicate with a ground or reference voltage plane, in which case the back side of the second semiconductor device may communicate with the ground or reference voltage plane upon being positioned against the spacers. Additional semiconductor devices may be added to the assembly. The first semiconductor device may be associated with a substrate. Assemblies and packages at least partially fabricated by the method are also disclosed.

Abstract: The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. In the semiconductor structure of the present invention, a dual trench isolation scheme is employed whereby a first trench isolation region of a first depth isolates devices of different polarity from each other, while second trench isolation regions of a second depth, which is shallower than the first depth, are used to isolate devices of the same polarity from each other. The present invention further provides a dual trench semiconductor structure in which pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane. In accordance with the present invention, the devices of different polarity, i.e., nFETs and pFETs, are bulk-like devices.

Abstract: A contact formed in accordance with a process for etching a insulating layer to produce an opening having an aspect ratio of at least 15:1 by first exposing the insulating layer to a second plasma of a second gaseous etchant comprising Ar, Xe, and combinations thereof to form an opening having an aspect ratio of less than 15:1. Secondly, the insulating layer is exposed to a first plasma of a first gaseous etchant having at least fifty percent helium (He) to etch the opening having an aspect ratio of at least 15:1, thereby increasing the aspect ratio to greater than 15:1, where the first gaseous etchant has a lower molecular weight than the second gaseous etchant.

Abstract: Disclosed are systems and methods for providing a real-time interactive surface. In one embodiment, such a system comprises an activity surface for use as a venue for an interactive experience, and an interactive experience control unit including an events management application. The events management application is configured to monitor and coordinate events occurring during the interactive experience. The system also comprises a surface rendering application interactively linked to the events management application, the surface rendering application configured to render a visual image for display at the activity surface in real-time, the visual image corresponding to one or more visual assets associated with a subset of the events occurring during the interactive experience.

Abstract: Improvements relating to a control device for controlling a display of a computer system for use with a video game includes a coordinate control unit for providing information related to a vertical and horizontal tilt of the control device, a game control unit for inputting game control information and a controller for processing the information provided by the coordinate control unit and game control unit. The vertical and horizontal point of view of the user in the video game and/or the vertical and horizontal position of a cursor on the display is determined based on the information related to the vertical and horizontal tilt of the control device. The control device is preferably shaped like a firearm to enhance the realism of the video game, and may include an LCD display mounted on the control device, as the primary display, and may also include an LCD mounted in a sighting device of the control device.

Abstract: Apparatus and methods to protect circuitry from moisture ingress, e.g., using a metallic structure as part of a moisture ingress barrier.

Abstract: A method of making a microelectronic package, and a microelectronic package made according to the method. The method includes: bonding and thermally coupling a plurality of IC dies to an IHS panel to yield a die-carrying IHS panel; mounting the die-carrying IHS panel onto a substrate panel including a plurality of package substrates to yield a combination including the die-carrying IHS panel mounted to the substrate panel; and singulating the combination to yield a plurality of microelectronic packages, each of the packages including: an IHS component of the IHS panel, one of the plurality IC dies bonded and thermally coupled to said IHS component and one of the plurality of package substrates, said IHS component and said one of the plurality of IC dies being mounted to said one of the plurality of package substrates to form said each of the packages.

Abstract: Methods of forming integrated circuit devices include forming an integrated circuit substrate having an electrically insulating layer thereon and forming a mask layer pattern having at least first and second openings of different size therein, on the electrically insulating layer. First and second portions of the electrically insulating layer extending opposite the first and second openings, respectively, are simultaneously etched at first and second different etch rates. This etching yields a first trench extending adjacent the first opening that is deeper than a second trench extending adjacent the second opening. Then, the bottoms of the first and second trenches are simultaneously etched to substantially the same depths using an etching process that compensates for the first and second different etch rates.

Abstract: In a horse race gaming machine 1, when a regular denomination process of S201 is executed, a regular BET image, wherein the minimum bet amount a player can specify is “1”, is displayed on a sub monitor 113 of a station 101. In the meantime, when a high denomination process of S208 is executed, a high BET image, wherein the minimum bet amount a player can specify is “2”, is displayed instead of the regular BET image, on the sub monitor 113 of the station 101. For executing the high denomination process of S208, for example, a player has to insert an IC card 119 into a reader/writer 118 (S203: YES), and further, the player has to touch a high button in the regular BET image of the sub monitor 113 (S207: YES).

Abstract: A multi-chip package type semiconductor device includes an insulating substrate having first and second conductive patterns thereon, a first semiconductor chip on the insulating substrate and having a first terminal pad and a relay pad isolated from the first terminal pad. The device further includes a second semiconductor chip on the first semiconductor chip having a second terminal pad. The first semiconductor chip is connected to the first pattern by a first bonding wire. The second semiconductor chip is connected to the second pattern by a second bonding wire, which connects the second pattern to the relay pad, and a third bonding wire, which connects the relay pad to the second terminal pad. The lengths of the first, second and third bonding wire are approximately the same.

Abstract: In a horse race gaming machine 1, a performance point is calculated on each of the player's racehorses, based on the results of respective racing games (S501). The number of wins, the number of races, a winning percentage, best time, etc. by the racehorses are taken into consideration when calculating the performance point. If the performance point satisfies a predetermined condition (S505: YES), a part or all of a jackpot prize amount is awarded to the player (S506). However, a side bet must be made for this racing game in order that a part or all of the jackpot prize amount is awarded to the player (S502: YES). Incidentally, to have a player's racehorse run in this racing game, there may be a case that the player is required to pay an entry point given to the player in accordance with BET amount specified by the player.

Abstract: A method of fabricating a semiconductor device including at least one of the following steps: forming an oxide layer on and/or over a silicon substrate. Forming a first photoresist pattern on and/or over the oxide layer. Forming a trench by etching the oxide layer and the substrate using the first photoresist pattern as a mask. Removing the first photoresist pattern. Filling the trench with a trench oxide layer. Planarizing the trench oxide layer. Forming an etch stop layer on and/or over the trench oxide layer. Forming a second photoresist pattern on and/or over the etch stop layer. Etching the etch stop layer and the trench oxide layer using the second photoresist pattern as an etch mask. Removing the second photoresist pattern and the etch stop layer.