Abstract: An electrical interconnect assembly for electrically interconnecting terminals on a first circuit member with terminals on a second circuit member. The electrical interconnect includes a housing having a plurality of through openings extending between a first surface and a second surface. A plurality of composite contacts are positioned in a plurality of the through openings. The composite contacts include a conductive member having a central portion and at least first and second interface portions. One or more polymeric layers extend along at least the central portion conductive member. One or more coupling features on the composite contacts engage with the housing. At least one engagement feature formed in the polymeric layers proximate the first interface portion mechanically couples with the terminals on the first circuit member.

Abstract: A semiconductor device includes a resin case, a plurality of external connection terminals fixedly provided on the resin case, and at least one semiconductor element provided in the resin case. At least one terminal block has at least one wiring terminal for electrically connecting the semiconductor element and the external connection terminals.

Abstract: A method of making a semiconductor chip assembly includes providing a post and a base, mounting a first adhesive on the base including inserting the post through an opening in the first adhesive, mounting a conductive layer on the base including aligning the post with an aperture in the conductive layer, providing a conductive trace that includes a pad, a terminal and a selected portion of the conductive layer, then flowing a second adhesive into and downward in a gap between the post and the conductive trace, solidifying the second adhesive, then mounting a semiconductor device on a heat spreader that includes the post and the base, electrically connecting the semiconductor device to the conductive trace and thermally connecting the semiconductor device to the heat spreader.

Abstract: A method for fabricating a low temperature polysilicon thin film transistor. The method includes steps of: first, a substrate is provided and a buffer layer is then formed over the substrate. Next, a low surface energy material layer is formed over the buffer layer and then a first amorphous silicon layer is formed on the low surface energy material layer, or on a buffer layer processed by hydrogen plasma. The first amorphous silicon layer is completely melted by a laser annealing step so that the liquid first amorphous silicon layer sequentially transforms into a number of polysilicon seeds being uniformly distributed on the low surface energy material layer. A second amorphous silicon layer is further formed over the low surface energy material layer and covers the polysilicon seeds.

Abstract: An apparatus for integrating wafer scale semiconductor integrated circuits and interfacing them with other systems. A wafer, partial wafer, die or plurality of same are mated to a printed circuit board (PCB) which electrically contacts the pads on each die using small conductive pillars. The PCB in turn is connected easily to other electronic systems. The entire apparatus is incorporated into other systems which utilize the dice in the apparatus. The apparatus may be fitted with heating elements and cooling channels to generate the necessary die temperatures for burn-in, testing, and operation. The apparatus is easily adaptable to include more dice in a stacked configuration.

Abstract: In a method of manufacturing an electronic component for forming a conductor pattern on an insulating substrate by transfer method employing intaglio printing technique, this manufacturing method comprises a step of fabricating an intaglio 20 made of flexible resin forming an insulating layer 23 on a groove 21, a step of filling the groove 21 with Ag paste 24 and drying, a step of overlaying the intaglio 20 on an insulating substrate 2 having a water-soluble resin 28 formed on the surface by pressing a pressing portion 26, freezing, peeling off the intaglio 20 and insulating substrate 2, and transferring the pattern of the Ag paste 24, and a step of firing it and forming a conductor pattern.

Abstract: A process for manufacturing a package of a semiconductor device, and providing a semiconductor device in which a vapor-impermeable moistureproof plate is embedded in a bottom surface of a hollow package or an inner surface wallthicknesswise therefrom to provide moisture-proofness.

Abstract: A fragile device, such as an integrated circuit chip or a multichip assembly, is packaged by first dispensing a sol surrounding the sides of the device. The sol is laterally confined by means of a rim member typically made of a pre-molded plastic material. The amount of the sol dispensed is not sufficient to run over the top of the rim member. The sol is then heated to form a gel. If desired, a cover member can be put into place onto the top surface of the rim member, for the purpose of additional mechanical protection of the fragile device, for example.

Abstract: Methods for forming solder bumps on terminal pads of a semiconductor substrate for an integrated circuit device employ a solder bump transfer plate and a mask to form solder deposits on the plate. One embodiment of the invention employs a metal mask having a plurality of through holes for forming solder deposits on the solder bump transfer plate by vapor phase deposition through the through holes each area of which increases in step wise from the first surface of the mask to the second surface opposite to the first surface, thereby preventing solder deposits in the through holes from being removed when the mask is separated from the plate. Another embodiment of the invention is a solder bump transfer plate having a plurality of solder deposits on the surface non-wettable to molten solder both diameter and spacing of which are both smaller than diameter and spacing of the terminal pads on the semiconductor substrate, whereby a single solder bump is accurately formed on each of the terminal pads.

Abstract: A method for producing a lead frame having outer leads and inner leads, for use in constructing a resin-sealed semiconductor package comprises etching processes for etching a blank. A first resist pattern having a first opening and a second resist pattern having second openings are formed on the first and the second major surfaces of a blank. The first and the second major surfaces of the blank are etched through the first and the second resist pattern by a first etching process using a first etchant to form a first recess corresponding to the first opening and second recesses corresponding to the second recesses in the first and the second major surfaces, respectively. The first recess is filled up with an etch-resistant layer. The second major surface is etched through the second resist pattern by a second etching process using a second etchant so that portions of the blank corresponding to the second openings of the second resist pattern are etched through to form the tips of the inner leads.

Abstract: A process for manufacturing semiconductor device including a heat sink adjacent to a die. A dam is positioned at the peripheral edges of the heat sink. During a transfer molding process, the dam serves two purposes. First, the dam prevents damage to the mold. Second, the dam prevents encapsulant packaging compound material from flowing onto the heat sink. The dam may be a gasket. The dam may also be a burr created by, for example, stamping the bottom of the heat sink. The dam may include copper, polyamides, and leadlock tape. The dam may be permanently connected to the heat sink or removed following packaging. The dam may be removed mechanically, through the use of heat, or during an electrolytic deflash cycle.

Abstract: A gas curtain for use with a semiconductor processing system to prevent unwanted gases from entering a processing chamber. The gas curtain includes both upward and downward flows of gas surrounding an isolation valve adjacent a delivery port into the processing chamber. In the valve open position, the downward flows extends between the valve and the delivery port, and the upward flow extends in an opposite direction behind the isolation valve. In the valve closed position, one of the flows extends through a slot in the isolation valve, while the other flow is directed in an opposite direction on the rear side of the isolation valve. In a method of using the gas curtain apparatus, a pick-up wand operating on a Bernoulli principal uses gases which are unwanted in the processing chamber, and just prior to loading wafers into the processing chamber, the gas flow in the Bernoulli wand is switched from a first gas to a second gas. Desirably, the second gas is hydrogen.

Abstract: Method for the preparation of electrodeposited or galvanically deposited bumps for the bonding of integrated circuits, characterized by two subsequent metal depositions, deposited without an external current source (chemical metal deposition) on a metallization 1, the first deposition being thicker than the second and the second deposition being more even or more regular throughout a large area than the first one.

Abstract: A method for flip-chip bonding an integrated circuit die to a substrate. The method includes the steps of providing the integrated circuit die with at least one gold bump, forming a barrier layer on the gold bump, forming a bronzing agent on the barrier layer, and providing the substrate with at least one conductive bonding area, which is also covered with gold. The bronzing agent on the integrated circuit die is then aligned on the conductive bonding area, and a compression force is applied to the die and substrate so as to establish contact between the bronzing agent and the conductive bonding area. While maintaining position between the gold bump and conductive bonding area, the structure is alloyed such that the bronzing agent and the gold on the conductive bonding area form an intermetallic compound, thereby forming a bond between the die and the substrate. The barrier layer functions to prevent the bronzing agent from diffusing with the gold bump.

Abstract: Discloses is an apparatus and method for cleaning the edges of semiconductor wafers by using a particle withdrawing means having pre-formed, low-tack adhesive material that removes the particles from the edges of the wafers and retains the particles thus removed.

Abstract: A process for manufacturing a multi-layer printed circuit board comprises a first metallic layer, a first Ta or Hf layer on one face of the first metallic layer, a first layer of Ta.sub.2 O.sub.5 or HfO on a face of the Ta or Hf layer opposite the first metallic layer, a second metallic layer on the Ta.sub.2 O.sub.5 or HfO layer opposite the Ta or Hf layer, a first dielectric layer on the first metallic layer opposite the Ta of Hf layer, and a second dielectric layer on the second metallic layer opposite the Ta.sub.2 O.sub.5 or HfO layer. A multi-layer printed circuit board is formed by adding the following layers to form the second capacitor. A third metallic layer on said second dielectric layer, a second Ta or Hf layer on a face of the third metallic layer, a second Ta.sub.2 O.sub.5 or HfO layer on a face of the second Ta or Hf layer opposite the third metallic layer, a fourth metallic layer on the second Ta.sub.2 O.sub.

Abstract: In a semiconductor integrated circuit consisting of a plurality of semiconductor chips each having a plurality of islands, two or more bonding wires each having different potential are connected to bonding pads formed on the surface of semiconductor chips. The islands are isolated by a dielectric isolation region comprising polysilicon film and isolation film formed in an isolation groove. The polysilicon film is exposed at a dicing line region around the semiconductor chip and a surface of the polysilicon film is made highly resistive. If two or more bonding wires come into contact with the polysilicon film exposed at a peripheral region of the semiconductor chip to cause short circuit, parasitic conductance does not occur between two or more bonding wires because the peripheral region of the semiconductor chip has high resistivity, whereby variation in characteristics of the semiconductor integrated circuit can be suppressed.

Abstract: Wafers from plural non-vacuum multiple wafer carriers are loaded and unloaded in an atmospheric front end of a wafer processing machine and transferred to and from the high vacuum chamber of a transfer module of a wafer manufacturing cluster tool through a plurality of single wafer loadlocks. Preferably, with the wafers oriented horizontally throughout, wafers are moved inbound to the high vacuum atmosphere through one loadlock and moved outbound through another loadlock, the outbound loadlock also actively cooling the wafer. In both the atmospheric and vacuum environments, transfer arms load and unload the loadlocks as often as possible when the other loadlock or loadlocks are sealed, and transfer wafers within the environments when all loadlocks are sealed. Preferably, the wafers are actively cooled in the outbound loadlock. Preferably also, wafers are passed through a wafer aligner after being removed from a carrier and before placed in a loadlock.

Abstract: In a circuit board/IC package assembly the die cavity in the IC package body portion is filled with a thermally conductive liquid to substantially facilitate the transfer of operational die heat toward the inner, lid side of the IC package that faces the circuit board. To dissipate the die heat received by the die cavity lid, a spaced series of metal-plated through holes are formed in the circuit board. The metal plating portions of the through holes are engaged with an internal ground plane structure within the circuit board, and are thermally coupled to the IC package die cavity lid. Accordingly, during operation of the IC package, die heat is conducted to the ground plane structure sequentially through the die cavity liquid, the cavity lid, and the metal-plated through holes.

Abstract: One lot is a group of wafers-to-be-processed in one wafer carrier, and one lot region for one lot is allocated fixed to a holding region of a wafer boat. A variable lot region mode in which lot regions for 4, for example, lots are allocated to the wafer boat. When a lot number is less than 4, or numbers of sheets of wafers-to-be-processed in the respective lots are less than a prescribed number, the lot regions can be compressed, centered on a number of a set holding groove is prepared. On the other hand, in connection with transfer of monitor wafers, a mode in which monitor wafers are transferred to inter-lot regions, and a mode in which numbers of holding grooves can be designated are prepared. The former mode is selected in product monitor, and the latter mode is selected in apparatus monitor.