Abstract: A process for manufacturing chip size semiconductor package with a light, thin, and compact structure having a reduced size of its semiconductor chip while having an increased number of pins For the package, it is possible to use either the semiconductor chip having bond pads arranged on end portions of the chip or the semiconductor chip having bond pads arranged on the central portion of the chip. In either case, input/output terminals of the package are arranged in the form of an area array. Accordingly, when the package is mounted on an electronic appliance, its mounting area can be minimized, thereby achieving a compactness of the final product.

Abstract: A thin-film microcircuit comprising fabricating a substrate of high-purity, densely packed alumina ceramic with a fine grain size, and metallization deposited thereon and applying a vacuum anneal to the metallization.

Abstract: A plurality of single crystal grains made of Bi.sub.2 Sr.sub.2 Ca.sub.1 Cu.sub.2 O.sub.8 which are heat treated at a temperature that is equal to or higher than the crystallization temperature of an oxide high-temperature superconductor made of Bi.sub.2 Sr.sub.2 Ca.sub.1 Cu.sub.2 O.sub.8 and are surrounded by a grain boundary are formed on a substrate made of a MgO single crystal. A convex portion having a sectional area of 400 .mu.m.sup.2 or less and a height which is equal to or less than ten times as much as a space between block layers of Bi.sub.2 Sr.sub.2 Ca.sub.1 Cu.sub.2 O.sub.8 is formed on the upper face portion of the single crystal grain. A first electrode made of Au is formed on the upper face of the convex portion of the single crystal grain, and a second electrode is formed in a region other than the convex portion in the single crystal grain. The first electrode is insulated from the second electrode by an insulating film made of CaF.sub.2.

Abstract: A process for manufacturing a metal plane support for making multi-layer lead frames adapted to be used for semiconductor devices. The lead frame support is made of a single thin metal strip having a plurality of lead frames continuously arranged in the longitudinal direction, the metal plane support is also made of a single thin metal strip and includes a plurality of metal planes, such as power supply planes, ground planes of the like, continuously arranged in the longitudinal direction corresponding to said plurality of lead frames. A pair of side rails are extending in the longitudinal direction for supporting the metal planes therebetween. The metal planes are connected to the rails via separating portions for removing the rails from the metal planes, after the metal planes are adhered to the corresponding lead frames.

Abstract: A process wherein a Au layer 3 and a Sn layer 5 are laminated on a barrier layer 8 which is formed on an optical circuit substrate 1. An Au layer 5 having a predetermined thickness is formed on the laminated layers as a top layer. A junction portion 2 is constituted of these layers. An electrode layer of an optical semiconductor element 9 is made to contact with the top Au layer 5 and the optical semiconductor element 9 is pressed to the optical circuit substrate 1. Then, by heating, the optical semiconductor element 9 is joined on the optical circuit substrate. A weight % of Au and Sn in the junction portion 2 of the optical circuit substrate 1 is about 80%:20% before the joining. The electrode layer is formed as a thin Au layer. The optical circuit substrate 1 is heated at a temperature of 280.degree. C. or more such that the Au layer and the Sn layer are melted and is cooled such that Au and Sn are solidified.

Abstract: A method for packaging semiconductor dice is provided. The package includes a thinned die mounted on a compliant adhesive layer to a substrate. The package is formed by providing a wafer containing a plurality of dice, thinning a backside of the wafer by etching or polishing, attaching the thinned wafer to the substrate, and then dicing the wafer. The semiconductor package can be mounted to a supporting substrate such as a printed circuit board in a chip-on-board configuration. The compliant adhesive layer and substrate of the package eliminate stresses and cracking of the die caused by a thermal mismatch between the die and supporting substrate. In addition, the semiconductor package can be mounted in a flip chip configuration with the substrate for the package protecting a backside of the die from radiation.

Abstract: A die attach procedure for SiC uses the scrubbing technique to bond a SiC die to a package. A first layer is formed on the SiC die. This first layer, preferably of nickel, bonds to the SiC die. A second layer, preferably amorphous silicon, is then formed on the first layer. The second layer bonds to the first layer, and forms a eutectic with the material, usually gold, plating the package when the SiC die is scrubbed onto the package.

Abstract: A method of fabricating vertically integrated microelectronic systems by CMOS-compatible standard semiconductor process technology, by independently processing individual component layers of at least two separate substrates, including the formation of via holes penetrating through all existing component layers and connecting together the front surfaces of the two substrates, thinning the reverse surface of one of the substrates down to the via holes, increasing the depth of the via holes to a metallization plane of the other substrate and forming electrically conductive connections between the two substrates through the via holes.

Abstract: A process for manufacturing a MOS-technology power device chip and package assembly, the MOS-technology power device chip comprises a semiconductor material layer in which a plurality of elementary functional units is integrated, each elementary functional unit contributing a respective fraction to an overall current and including a first doped region of a first conductivity type formed in the semiconductor layer, and a second doped region of a second conductivity type formed inside the first doped region; the package comprises a plurality of pins for the external electrical and mechanical connection; the plurality of elementary functional its is composed of sub-pluralities of elementary functional units, the second doped regions of all the elementary functional units of each sub-plurality being contacted by a same respective metal plate electrically insulated from the metal plates contacting the second doped regions of all the elementary functional units of the other sub-pluralities; each of the metal plates

Abstract: A method for manufacturing of a lead-on-chip type semiconductor chip package is disclosed, which comprises the steps of coating a liquid polyimide coating material on the bonding faces of at least one of the inner leads and the bus bars of the lead frame and the semiconductor chip, attaching the semiconductor chip by using the cured liquid polyimide coating material as an attaching medium, and forming a package body for wrapping and protecting the semiconductor chip and bonding wires. Since the liquid polyimide coating material protects the wafer from which the chips are obtained and also serves as a bonding agent for the semiconductor chip at the same time, the semiconductor chip package according to the present invention can be protected from damage, such as by air bubbles, which are generated at the interface of the conventional polyimide tape, and by separation and expansion of adhesives.

Abstract: The substrate unloaded from the exposure device is received at the interface unit, and then carried by the substrate carrying means to the heat treatment unit, where a heat treatment is carried out on the substrate. After that, the substrate is carried from the heat treatment unit to the cooling unit, where the substrate is cooled. After the completion of the cooling process, the substrate is carried by the carrying means from the cooling unit to the development unit, where the resist film on the substrate is developed. In this resist process, the required time for the process at the heat treatment unit is changed in accordance with the required time for the process at the exposure unit. The required time for the process at the heat treatment unit is equalized with the required time for the process at the exposure device. The required time for the process at the heat treatment process is changed by prolonging or shortening the pre-process at the heat treatment unit.

Abstract: A process for laser processing an article, which comprises: heating the intended article to be doped with an impurity to a temperature not higher than the melting point thereof, said article being made from a material selected from a semiconductor, a metal, an insulator, and a combination thereof; and irradiating a laser beam to the article in a reactive gas atmosphere containing said impurity, thereby allowing the impurity to physically or chemically diffuse into, combine with, or intrude into said article.

Abstract: In the fabrication of an integrated circuit having both N MOSFETs and P MOSFETs in which the respective N-type species and P-type species have substantially different diffusivities, the source implant of the dopant species having a the higher diffusivity is advantageously delayed until a contact masking process step. By delaying the dopant species having the higher diffusivity, depletion of the dopant by subsequent annealing steps is avoided. P MOSFETs formed using a high diffusivity boron implant species in an integrated circuit including both P MOSFETs and N MOSFET are fabricated with no source implant in the source regions during formation of the gate electrodes and sidewall spaces.

Abstract: The electronic component (10) has a die (22) and a terminal (14) coupled to the die (22). The substrate has a first side (20) and a second side (82) and a passage (26) therethrough. The terminal (14) is in communication with the first side (20) and the die (22) is disposed within the passage (26). The apparatus includes a cover (16) which encloses the die (22) and a portion of the terminal (14), and has a fixed portion (28) and a removable portion. The fixed portion (28) includes a connection region coupled to the terminal (14) and an extension region disposed within the passage (26). The extension region has a surface that is substantially coplanar with the second side (82). There is a space (32) between the extension region and the substrate (18). An adhesive (34) is disposed on the surface of the extension region, extending into the space (32). A sealing frame (36) overlaps the space (32) and is in communication with the adhesive (34) and the second side (82).

Abstract: A circuit substrate connection method for assuring to connect the semiconductor parts or sub-circuit substrate to a main circuit substrate such as liquid crystal display panel by avoiding a short between the electrodes on the same substrate. In the present invention, photosensitive resin including conductive particulates is painted on the transparent circuit substrate, and a light is radiated from the bottom of the main circuit substrate. As the electrode of the circuit substrate shields the light, the conductive particulates are removed together with the photosensitive resin other than on the electrode by developing the main circuit substrate. Further, in the present invention, the photosensitivity resin is painted on the transparent main circuit substrate, the photosensitivity resin on the electrode on the main circuit substrate are removed, the conductive particulates are filled in the removed portion, and thus only the conductive particulates are arranged only on the electrodes.

Abstract: A FET is formed that occupies a reduced surface area on a substrate because it incorporates elevated source/drain contacts provided at least partially over the field oxide regions. A silicon nitride mask is formed over the substrate and the mask is used for defining field oxide regions. Trenches are etched on either side of the mask and then thermal oxidation grows field oxide regions in the trenches so that the surface of the field oxide regions are approximately even with the original surface of the substrate. With the silicon nitride mask still in place, polysilicon is deposited over the substrate. The device is then planarized to remove the polysilicon from surfaces of the substrate, exposing the surface of the mask and leaving polysilicon structures on the field oxide regions on either side of mask. The mask is stripped and a layer of silicon is deposited over the polysilicon structures and on the active device region of the substrate, where the deposited silicon is epitaxial.

Abstract: A process wherein a lead frame into which a plurality of semiconductor devices are integrated is first supplied to a press unit (21) among three press units (21 to 23) for cutting, to be cut into the respective semiconductor devices. Thereafter the lead frame is successively fed to the press units (22, 23) in the units of the semiconductor devices due to the action of an internal conveyor (33a), thereby being subjected to cutting stepwise. Thus, the press units (21 to 23) are provided at wide spaces, whereby press motors (85a to 85c) requiring high outputs are independently set for the respective press units (21 to 23). Further, the process does not vary the space between molds with the product pitch of the lead frame. Working is enabled by the press motors which are provided for the respective press units. The process copes with various types of semiconductor devices because the space between the molds may not be changed.

Abstract: A tape carrier structure (T1,T2) for a tape carrier package on which at least one semiconductor chip (1) is mounted, the tape carrier structure (T1,T2) having a polyimide tape (3) and leads (2) joined onto the polyimide tape (3), an end of each of the leads (2) being connected to one of connecting pads corresponding thereto, the connecting pads being provided on the semiconductor chip (1), wherein the polyimide tape (3) has a facing portion (3a) which is situated so as to face to the semiconductor chip (1) except the connecting pads on condition that the semiconductor chip (1) is mounted on the tape carrier package.

Abstract: A process for manufacturing a lead frame (10) connected over an integrated circuit (40) by adhesives (42) and (44). Each lead conductor (16) and (18) of the lead frame (10) has the identical geometric area in order to provide identical capacitances. A metal shield may be provided on adhesives (42) and (44) to provide noise shielding for the integrated circuit (40).

Abstract: A process for manufacturing a vacuum enclosure for a semiconductor device formed on a substrate with leads extending peripherally. Assembly of the enclosure is compatible with known batch fabrication techniques and is carried out at pressures required for optimal device operation. In a first embodiment, an intrinsic silicon shell is sealed to the substrate via electrostatic or anodic bonding with the leads diffusing into the shell. In a second embodiment, a thin interface layer of silicon or polysilicon is deposited on the substrate prior to electrostatic bonding a glass shell thereon. In a third embodiment, tunnels are formed between a lower peripheral edge of the shell and the substrate, allowing leads to pass thereunder. The tunnels are sealed by a dielectric material applied over the enclosure.