Abstract: A substrate processing system comprises a cassette mounting section having a plurality of cassettes arranged therein, a sub-arm mechanism for transferring the substrate into and out of the cassette within the cassette mounting section, a first transfer path of the sub-arm mechanism extending along the arrangement of the cassettes in the cassette mounting section, a process section including a heat treating section for heating or cooling the substrate and a liquid treating section in which a process liquid is applied to the substrate, a main arm mechanism for transfer of the substrate from and onto the sub-arm mechanism and from and into the process section, and a second transfer path of the main arm mechanism. The heat treating section is positioned higher than the first transfer path, interposed between the cassette mounting section and the second transfer path in respect of a horizontal plane, and comprises a plurality of compartments stacked one upon the other.

Abstract: Apparatus and concomitant method for performing priority based scheduling of wafer processing within a multiple chamber semiconductor wafer processing system (cluster tool). The sequencer assigns priority values to the chambers in a cluster tool, then moves wafers from chamber to chamber in accordance with the assigned priorities. The sequencer is capable of determining the amount of time available before a priority move is to be performed and, if time is sufficient, the sequencer performs a non-priority move while waiting. The sequencer also dynamically varies assigned priorities depending upon the availability of chambers in the tool. Lastly, the sequencer prioritizes the chambers based upon the minimum time required for the robot to move the wafers in a particular stage.

Abstract: A method for producing a semiconductor device includes steps of: a) a positioning board forming process in which concave portions, each of which is located at a position corresponding to a position of a respective projecting electrode of a semiconductor device, and first positioning portions, which are used for determining a position of a sealing resin with respect to the projecting electrode, are integrally formed on a flat-plate member so as to form a positioning board; b) a filling process in which an electrode material for forming the projecting electrode is filled in the concave portions formed on the positioning board; c) a bonding process in which a composite board is formed by mounting a circuit board on the positioning board so as to bond each of the electrode material filled in the concave portions to the circuit board; d) a sealing resin forming process in which a mold having a cavity for forming a sealing resin and second positioning portions for determining a position of the positioning board wit

Abstract: A method is provided for depositing aluminum thin film layers to form contacts in a semiconductor integrated circuit device. All or some of the deposition process occurs at relatively low deposition rates at a temperature which allows improved surface migration of the deposited aluminum atoms. Aluminum deposited under these conditions tends to fill contact vias without the formation of voids. The low temperature deposition step can be initiated by depositing aluminum while a wafer containing the integrated circuit device is being heated from cooler temperatures within the deposition chamber.

Abstract: A processing apparatus comprises a plurality of process unit groups each including a plurality of process units for subjecting an object to a series of processes, the process units being arranged vertically in multiple stages, an object transfer space being defined among the process unit groups, and a transfer mechanism for transferring the object, the transfer mechanism having a transfer member vertically movable in the object transfer space, the transfer member being capable of transferring the object to each of the process units. The processing apparatus further comprises a mechanism for forming a downward air flow in the object transfer space, a mechanism for controlling the quantity of the downward air flow, and a mechanism for controlling the pressure in the object transfer space. Thus, a variation in condition of the object transfer space is reduced.

Abstract: A lead-on-chip semiconductor device package is formed by attaching a lead frame to the chip with a discontinuous adhesive layer. Electrode pads of the chip are electrically connected by bonding wires and mechanically connected by the adhesive layer to the lead frame, and then encapsulated by an encapsulant such as molding compound. The adhesive layer is formed from a liquid adhesive material having a certain viscosity. Although the liquid adhesive is continuously applied to top surfaces of the inner leads as well as gaps between adjacent inner leads, the adhesive layer is formed only on the top surfaces of the inner leads while the liquid adhesive falls through the gaps. Thermoplastic or thermosetting resins may be used as the liquid adhesive.

Abstract: An apparatus (400) enclosing a portion of a substrate (401) is used for affixing at least one component to a corresponding circuit of the substrate when a manufacturing line (800) ceases to operate. The apparatus includes a conveyor (400), heating elements (102), and a controller (816) for controlling operation of the apparatus (400). The conveyor is used for indexing the substrate periodically through the apparatus. The heating elements are used for dividing the portion of the substrate enclosed by the apparatus into controllable temperature zones (902). The controller is adapted to cause each of the plurality of heating elements to dynamically adjust the temperature of each of the controllable temperature zones upon the indexing process of the manufacturing line (800) ceasing to operate, until at least one component of each circuit enclosed by the apparatus has been adequately affixed to its corresponding circuit.

Abstract: A semiconductor chip scale package and method of producing the package are disclosed. The package has a semiconductor chip having signal leading bumps. A PCB is electrically connected to the chip, thus transmitting input and output signals. A plurality of solder balls are formed on the lower surface of the PCB and are used as signal input and output terminals. An epoxy resin layer bonds the chip to the PCB. The PCB consists of a polymer resin substrate, a copper circuit pattern and a solder mask. The copper circuit pattern has a chip bump land and a solder ball land. The lands electrically connect the signal leading bumps to the solder balls. The package has a package size being similar to or slightly larger than a semiconductor chip within 120 % of the size of the chip.

Abstract: A method of manufacturing a semiconductor integrated circuit device includes the steps of constructing a plurality of lead frames having leads which each include an inner portion and an outer portion and electrically connecting a semiconductor chip to the inner portions of the leads of each frame. The lead frames are then stacked one above each other to form a vertical stack and plates are then inserted between each of the lead frames with each plate having an opening in the center whereby a central cavity is formed in the stack. The stack is then placed between a top mold member and a bottom mold member and a resin is injected into the central cavity whereupon the resin is cured to form a single resin package encapsulating the semiconductor chips. The resin package is then released from the mold members.

Abstract: A method of forming chip bumps of a bump chip scale semiconductor package, such a package and a chip bump are disclosed. In the bump chip scale semiconductor package produced by the above method, the chip bumps are directly formed on the chip pads of a semiconductor chip. The above chip bumps are used as the signal input and output terminals of the package and are used as surface mounting joints when the chip is mounted to a mother board.

Abstract: A process for manufacturing a semiconductor device assembly including a semiconductor device having a plurality of bond pads on the active surface thereof and a lead frame having a portion of the plurality lead fingers of the lead frame located below the semiconductor device in a substantially horizontal plane and another portion of the plurality of lead fingers of the lead frame located substantially in the same horizontal plane as the active surface of the semiconductor device. Both plurality of lead finger of the lead frame having their ends being located substantially adjacent the peripheral sides of the semiconductor device, rather than at the ends thereof.

Abstract: A method of producing a packaged semiconductor integrated circuit including hardened resin packaging and a polished electrode including producing external electrodes on a wafer including an IC chip employing photolithography in a process for producing an IC chip; depositing and hardening resin on the wafer; polishing the wafer to clean the external electrodes; and cutting the wafer and separating the resulting chips from the wafer, thereby producing a flip-chip package.

Abstract: A process for producing a metal foil-covered semiconductor device. The metal foil material is one which is, in molding a resin for encapsulating a semiconductor element using a mold, temporarily fixed on a surface of a cavity of the mold, and is adhered on a surface of a semiconductor device by injecting the encapsulating resin into the mold and molding the resin, wherein a contact angle of the face of the metal foil material which is in contact with the encapsulating resin during molding, to water is 110.degree. or less.

Abstract: A method for producing a capacitor includes: a dielectric body composed of basic alumina powder mixed with tungsten powder, interposed between a pair of electrodes disposed opposite to each other. The method includes the steps of: after a conductive alumina ceramic body has been formed by mixing the tungsten powder with the alumina powder, providing a pair of electrodes while interposing the conductive alumina ceramic body therebetween, and intermittently applying an electric current or voltage to the electrodes, high enough to break conductive paths formed in the conductive alumina ceramic body by the tungsten powder, so that the conductive ceramic body is converted to the dielectric body.

Abstract: A laser diode package includes a laser diode, a heat sink and a lid. The laser diode has an emitting surface, a reflective surface opposing the emitting surface, and first and second surfaces between the emitting surface and the reflective surface. The laser diode has a diode height defined between the emitting surface and the reflective surface. The heat sink has an interior surface, an exterior surface opposing the interior surface, a top surface and a base surface. The height of the heat sink is defined between the top surface and the base surface and is approximately less than four times the laser diode height. The first surface of the diode is attached to the interior surface of the heat sink with a first solder. The base surface of the heat sink is coupled to a thermal reservoir. The lid is attached to the second surface of the laser diode via a second solder. An upper end of the lid is near the emitting surface of the laser diode.

Abstract: A thermoelectric power generation unit comprises a plurality of dissimilar thermoelectric structures (20, 21) laid in alternating layers. Adjacent thermoelectric bodies incorporated in each of the thermoelectric structures are connected together in series. Respective thermoelectric structures are fabricated by the steps of forming a stripe-shaped pattern on a substrate (10) using a photosensitive resin (12), forming a polymer film on the underside of the substrate, forming first thermoelectric bodies (15) and second thermoelectric bodies (17) by plating on an electrode film (11) inside openings of the photosensitive resin, coating the first thermoelectric bodies (15) and second thermoelectric bodies (17) with a thermosetting resin (16), dissolving the substrate (10) and electrode film (11) thereafter.

Abstract: In a method of manufacturing a semiconductor device comprising a semiconductor chip and a carrier film which includes an insulating film and wiring patterns formed on one of main surfaces of the insulating film, an adhesive layer is formed on a surface of a semiconductor wafer having a number of integrated circuits. Each of the integrated circuits has electrode pads for external connection on the foregoing surface of the semiconductor wafer. Subsequently, openings are formed at regions of the adhesive layer corresponding to the electrode pads, and then, the semiconductor wafer is cut per integrated circuit so as to obtain the semiconductor chips. Thereafter, the electrode pads of the semiconductor chip and the wiring patterns of the carrier film are connected to each other through the corresponding openings of the adhesive layer, respectively. Then, the semiconductor chip and the carrier film are bonded together via the adhesive layer interposed therebetween.

Abstract: An electronic device includes at least one chip connected to a circuit board. The chip includes a die and an encapsulant which is applied in a liquid phase and dries to a solid phase. A shell may be positioned over the chip and in some embodiments of the invention extends over the entire device. A dam is connected to the circuit board adjacent the die in at least one direction so as to restrain flow of the encapsulant toward the dam when the encapsulant is in the liquid phase. The dam may include an upper end at an elevation higher than the uppermost portion of the chip (which would usually be encapsulated), the dam acting as a standoff between the shell and the chip. The upper end of the dam may be constantly in contact with the shell or, alternatively, the upper end of the dam may be ordinarily not in contact with the shell, but comes into contact with the shell if the shell is compressed or flexed toward the chip. A single dam may surround the die (and chip structure after the encapsulant dries).

Abstract: A manufacturing method for a semiconductor unit which is capable of reducing the generation of a camber of a base member and enhancing reliability in operation.

Abstract: A method of fabricating an electrical interconnect are provided. A first transparent dielectric layer is disposed on top of a support structure. A conductive circuit layer is plated above the first dielectric layer. Separate conductive layers are plated on top of the conductive circuit layer to produce conductive vias. A second transparent dielectric layer is disposed around the conductive layers. Contact tips are electrically connected to the top surface of the separate conductive layers. The interconnect may be visually aligned so that the contact tips brought into contact with target connections. In addition, the support structure may be partially removed to allow a flexible interconnect.