Abstract: Buffers of programmable depths are used in the instruction and reply paths of cascaded devices to account for possible differences in latencies between the devices. The buffers may be enabled or bypassed such that the alignment of instruction and result may be performed at the boundaries between separate groups of devices having different instruction latencies.

Abstract: In one embodiment of the invention, a replaceable memory apparatus is disclosed. The replaceable memory apparatus includes a first rectangular multilayer printed circuit board having a first side and a second side opposite the first side; a first male pluggable electrical connector mounted to the first side near a first edge; a first female pluggable electrical connector mounted to the second side; and first non-volatile memory mounted to the first side and the second side. The first female pluggable electrical connector is coupled to the first male pluggable electrical connector to feed through first signals. The first non-volatile memory is coupled to the first female pluggable electrical connector and the first male pluggable electrical connector to receive the first signals.

Abstract: A method for accessing a Universal Serial Bus (USB) device attached to the home gateway is provided to solve the problem that after the USB device is attached to the home gateway, the USB device becomes an exclusive device of the home gateway, and application software on a personal computer (PC) or other terminals can not be directly used to transparently access the USB device. The method includes: receiving a USB message of the USB device attached to the home gateway; and adapting the USB message to a network packet and sending the network packet to a virtual USB device interface of a terminal to be read by an application program of the terminal; or parsing a network packet sent by the terminal through the virtual USB device interface into a USB data frame and writing the USB data frame into the USB device.

Abstract: An embodiment may include circuitry to facilitate, at least in part, a first network interface controller (NIC) in a client to be capable of accessing, via a second NIC in a server that is remote from the client and in a manner that is independent of an operating system environment in the server, at least one command interface of another controller of the server. The command interface may include at least one controller command queue. Such accessing may include writing at least one queue element to the at least one command queue to command the another controller to perform at least one operation associated with the another controller. The another controller may perform the at least one operation in response, at least in part, to the at least one queue element. Many alternatives, variations, and modifications are possible.

Abstract: A switch device that allows a user to use the same non-Bluetooth user console (e.g., keyboard, mouse) to control both non-Bluetooth computers and Bluetooth master machines such as tablet computers, smart phones, etc. The switch device includes a console port for connecting to the console and one or more computer ports for connecting to one or more computers, as well as a Bluetooth module for communicating with Bluetooth master machines. A controller processes input device data received via the console port, and either sends the data to a selected Bluetooth master machine or a selected computer, or perform other functions such as switching, Bluetooth device pairing and disconnecting based on the input device data. The controller stores link information of the Bluetooth master machines already paired with the computer switch for quickly switching to a Bluetooth master machine. The switch device can be with or without video switching.

Abstract: A USB device enumeration process implemented in a USB device is described. The USB device first detects a type of the operating system (OS) of the USB host connected to the device, and performs device enumeration using a process selected from multiple stored processes based on the detected host OS type. To detect the host OS type, the USB device first presents itself to the host as a USB MSD or HID, performs device enumeration to collect OS behavior factors from the host, and determines the OS type from the OS behavior factors. Thereafter, the USB device performs actual device enumeration by presenting itself as the USB device it actually is, using an enumeration process specific to the detected host OS type. The multiple stored enumeration processes are customer configurable. Further, a method is provided to stop an enumeration process when the host is in a BIOS stage.

Abstract: Methods and structure for transferring administrative information through a communication interface. Features and aspects hereof provide for exchanging administrative information between an initiator device and a target device using read and write commands encoded with a reserved sub-tag value. In the context of a Serial Advanced Technology Attachment (SATA) system, a portion of a parameter (e.g., the LBA parameter) of a read or write command (a Native Command Queuing command) is defined to encode a sub-tag value. One or more sub-tag values are reserved to indicate that the corresponding read or write command is related to the exchange of administrative information rather than the reading or writing of data on a storage device. A parameter value encoded in the LBA field or data length field of the read or write command indicates administrative data to be returned to the initiator or to be updated within the target device.

Abstract: In one embodiment of the invention, a replaceable memory apparatus is disclosed. The replaceable memory apparatus includes a first rectangular multilayer printed circuit board having a first side and a second side opposite the first side; a first male pluggable electrical connector mounted to the first side near a first edge; a first female pluggable electrical connector mounted to the second side; and first non-volatile memory mounted to the first side and the second side. The first female pluggable electrical connector is coupled to the first male pluggable electrical connector to feed through first signals. The first non-volatile memory is coupled to the first female pluggable electrical connector and the first male pluggable electrical connector to receive the first signals.

Abstract: The present invention is directed to a method which allows for substitution of standard SAS ALIGN primitives with an alternative, more spectrally pure set of SAS ALIGN primitives that allows for enhanced continuous adaptation performance. Two consenting SAS devices which are connected to each other may negotiate for and start communicating using the alternate set of ALIGN primitives, which may allow for improved jitter tolerance and reduced bit error rate.

Abstract: In one embodiment of the invention, a replaceable memory apparatus is disclosed. The replaceable memory apparatus includes a first rectangular multilayer printed circuit board having a first side and a second side opposite the first side; a first male pluggable electrical connector mounted to the first side near a first edge; a first female pluggable electrical connector mounted to the second side; and first non-volatile memory mounted to the first side and the second side. The first female pluggable electrical connector is coupled to the first male pluggable electrical connector to feed through first signals. The first non-volatile memory is coupled to the first female pluggable electrical connector and the first male pluggable electrical connector to receive the first signals.

Abstract: A storage device includes a storage media storing an information structure for establishing a bidirectional communication layer and a controller configured to send the information structure to an external device according to an information structure read/write command. A layer for a bidirectional communication between the storage device and the external device is formed according to the information structure.

Abstract: A method for validating outsourced processing of a priority queue includes configuring a verifier for independent, single-pass processing of priority queue operations that include insertion operations and extraction operations and priorities associated with each operation. The verifier may be configured to validate N operations using a memory space having a size that is proportional to the square root of N using an algorithm to buffer the operations as a series of R epochs. Extractions associated with each individual epoch may be monitored using arrays Y and Z. Insertions for the epoch k may monitored using arrays X and Z. The processing of the priority queue operations may be verified based on the equality or inequality of the arrays X, Y, and Z. Hashed values for the arrays may be used to test their equality to conserve storage requirements.

Abstract: An integrated circuit of a hard disk drive includes an Ethernet network interface module configured to transmit and receive data packets via an Ethernet connection. The data packets respectively include packet headers and at least one of small computer system interface (SCSI) commands and SCSI data requests. A processor is configured to process the data packets transmitted and received by the Ethernet network interface module. A hard disk control module is configured to control, based on the at least one of the SCSI commands and the SCSI data requests, writing of data to a hard disk and reading of the data from the hard disk. Each of the hard disk control module, the processor, and the network interface module is located in the integrated circuit.

Abstract: A signal associated with multiple haptic effects is received, each haptic effect from the multiple haptic effects being associated with a time slot from multiple time slots. Each haptic effect from the multiple haptic effects is associated with an effect slot from multiple effect slots at least partially based on the time slot associated with that haptic effect. An output signal is sent for each effect slot from the multiple effect slots, when the associated haptic effect is scheduled for its time slot.

Abstract: Embodiments operating shared peripherals in a hybrid computing system are described. Embodiments control a shared wireless antenna variously between a primary system and a secondary system, where the secondary system is detachable from the primary system and operates as an independent computing device in the disconnected state, while operating as a display device in the connected state.

Abstract: Various embodiments include a method for regulating operation of mobile applications executing on a nomadic device. Signals for determining a speed of travel may be received at the nomadic device. The speed may be determined based on the one or more signals. If the determined speed exceeds a speed threshold, a speed restriction flag may be set and one or more functions of the mobile applications may be restricted. If, after setting the speed restriction flag, a speed cannot be determined, the application functions may be continually restricted until a speed can be determined.

Abstract: Memory devices and methods are described and shown that are capable of being configured in a chain. In one configuration, a single data input port and a single data output port are utilized at a host to communicate with the chain of memory devices. Methods for assigning identifiers to memory devices in the chain are described that include detection of a presence or absence of downstream memory devices. In selected examples, identifiers are assigned sequentially to memory devices in the chain until no additional downstream memory devices are detected.

Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Abstract: A method for exchanging peripheral data and submodule, wherein a transfer means is embedded into an operating system of the submodule for the exchange of the peripheral data with a main module to accelerate a process of copying input/output data from a decentralized peripheral system to a superordinate level.

Abstract: A computer implemented method includes receiving a request to access a configuration space that is associated with a virtual function. The request may include a configuration space address and a root complex identifier. The computer implemented method may include identifying a root complex based on the root complex identifier. The computer implemented method may also include selecting a slot that is associated with the root complex. The slot may be capable of coupling a hardware input/output adapter to the root complex. The computer implemented method may further include determining whether the configuration space address is associated with the selected slot. The computer implemented method may include accessing the configuration space using an access mechanism in response to determining that the configuration space address is associated with the selected slot.