Abstract: In one embodiment of the invention, a memory apparatus for improved write performance is disclosed. The memory apparatus includes a base printed circuit board (PCB) having an edge connector for plugging into a host server system; a card level power source to provide card level power during a power failure; a memory controller coupled to the card level power source and having one or more memory channels; and one or more non-volatile memory devices (NVMDs) coupled to the card level power source and organized to respectively couple to the memory channels controlled by the memory controller. Each memory controller provides queuing and scheduling of memory operations on a channel for each NVMD in the memory channels. Responsive to power failure, the memory controller receives card level power and changes the scheduling of memory operations to the NVMDs in each memory channel.

Abstract: In embodiments of extensions for USB driver interface functions, a set of USB driver interfaces are exposed by a USB core driver stack, and the USB driver interfaces include USB driver interface functions to interface with USB client function drivers that correspond to client USB devices. A composite device driver registers itself and requests a function handle for each function of a client USB device. The USB client function drivers are enumerated and the function handles generated for each function of the client USB device. A check first protocol is enforced that directs a USB client function driver to check for availability of a USB driver interface function before interfacing with the USB core driver stack via the USB driver interfaces. A contract version identifier is received that indicates a set of operation rules by which a USB client function driver interfaces with the USB core driver stack.

Abstract: The computer system includes a server being configured to manage a first virtual machine to which a first part of a server resource included in the server is allocated and a second virtual machine to which a second part of the server resource is allocated. The computer system also includes a storage apparatus including a storage controller and a plurality of storage devices and being configured to manage a first virtual storage apparatus to which a first storage area on the plurality of storage devices is allocated and a second virtual storage apparatus to which a second storage area on the plurality of storage devices is allocated. The first virtual machine can access to the first virtual storage apparatus but not the second virtual storage apparatus and the second virtual machine can access to the second virtual storage apparatus but not the first virtual storage apparatus.

Abstract: Described herein are systems and methods for device management, and more particularly systems and methods for auto addressing in a control network. For example, some embodiments relate to procedures and protocols implemented in the context of a building management system thereby to allow auto addressing of IO devices. In one embodiment, each IO device includes a respective engineering data key (EDK), which is indicative of device data such as the device type and function. This EDK is combined with a generated number thereby to define a device identification code that has significant chances of uniqueness. The device identification code is communicated to a controller to which the IO device connects in a bus-based topology. The controller uses the identification code to assign a network address to the IO device, using a stored repository of network addresses available for such assignment.

Abstract: Methods and systems for migrating data between storage tiers may include various operations, including, but not limited to: determining at least one activity index of at least one data storage region; receiving an input/output request addressing at least one data segment included in the at least one data storage region; qualifying a data segment addressed by the input/output request for migration to at least one higher-performing storage device; and adding a data segment reference associated with a qualified data segment to a priority queue according to the at least one activity index.

Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Abstract: According to one embodiment, a command management device includes a command buffer, a free address register and a FIFO unit with entries. The command buffer stores commands received from a host. The entries include address sections configured to store addresses of the areas in the command buffer in which the respective commands are stored. The address sections are connected together like a ring. Each of the address sections includes a substitute module configured to substitute either the free address held in the free address register or a second address stored in the address section preceding the each of the address sections for a first address stored in the each of the address sections.

Abstract: Methods and apparatuses for flushing write-combined data from a buffer within a memory to an input/output (I/O) device.

Abstract: A method of enabling access to resources includes detecting an input to access a resource of a multi-mode processing module coupled to a host processor and a control module. The method can further include detecting an operating mode of the host processor and the control module and an availability of independent peripheral resources of the multi-mode processing module. Additionally, the method can enable the multi-mode processing module in response to the detecting the operating mode and the availability of the independent peripheral resources.

Abstract: A client system using a virtual machine includes: a physical server that includes a CPU, a memory, a bus, and a plurality of bus adapters, manages a plurality of guest OS by a host OS, and operates as a virtual machine. A plurality of input and output units are coupled to the plurality of bus adapters of the physical server respectively. A host OS of the physical server includes a configuration definition table that stores identification numbers of the input and output units in correspondence to guest OSs used by the input and output units. The host OS notifies a guest OS corresponding to an input unit of input instruction information from the input units with reference to the configuration definition table and outputs a processing result of a guest OS to an output unit corresponding to the guest OS.

Abstract: Methods and apparatus for enhancing efficiency (e.g., reducing power consumption and bus activity) in a data bus. In an exemplary embodiment, methods and apparatus for intelligently trimming (and adding or re-adding) queue heads resident in a host device associated with various client device processes are disclosed. By selectively trimming inactive or dormant queue heads, the host expends less resources and time polling the queue heads during routine operations. Similarly, queue heads which are newly active, or acquired are intelligently added to ensure proper bus operation. Inactive queue heads are brought back into the polling process only when requested, thereby keeping the list of queue heads to be polled or examined as short as possible at all times.

Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Abstract: In one embodiment of the invention, a memory apparatus for improved write performance is disclosed. The memory apparatus includes a base printed circuit board (PCB) having an edge connector for plugging into a host server system; a card level power source to provide card level power during a power failure; a memory controller coupled to the card level power source and having one or more memory channels; and one or more non-volatile memory devices (NVMDs) coupled to the card level power source and organized to respectively couple to the memory channels controlled by the memory controller. Each memory controller provides queuing and scheduling of memory operations on a channel for each NVMD in the memory channels. Responsive to power failure, the memory controller receives card level power and changes the scheduling of memory operations to the NVMDs in each memory channel.

Abstract: A display apparatus operable in plural modes and a mode changing method thereof are disclosed. The display apparatus includes a storage unit which stores information about a final mode, and a controller which changes a mode of the display apparatus to the final mode and displays a corresponding screen if the display apparatus is connected to a host device.

Abstract: The object of the present invention is to provide a technique in which, in a storage apparatus using a PCI Express switch in an internal network, an EP can be shared among processors even if the EP is incompatible with the MR-IOV. A storage apparatus according to the present invention is provided with a first interface device which controls data input/output to and from a higher-level apparatus, and the first interface device is further provided with multiple virtual function units which provide virtual ports. The first interface device enables any of the virtual function units and does not enable any of the other virtual function units (see FIG. 14).

Abstract: A computer-implemented method for interconnecting a peripheral device and an electronic system includes analyzing an information (INF) file associated with the peripheral device, recognizing a resource conflict between the peripheral device and the electronic system based on the analyzing of the INF file, and resolving the resource conflict by modifying the INF file.

Abstract: Methods and systems to implement a physical device to differentiate amongst multiple virtual machines (VM) of a computer system. The device may include a wireless network interface controller. VM differentiation may be performed with respect to configuration controls and/or data traffic. VM differentiation may be performed based on VM-specific identifiers (VM IDs). VM IDs may be identified within host application programming interface (API) headers of incoming configuration controls and data packets, and/or may be looked-up based on VM-specific MAC addresses associated with data packets. VM IDs may be inserted in API headers of outgoing controls and/or data packets to permit a host computer system to forward the controls and/or packets to appropriate VMs. VM IDs may be used look-up VM-specific configuration parameters and connection information to reconfigure the physical device on a per VM basis. VM IDs may be used look-up VM-specific security information with which to process data packets.

Abstract: A communication system includes a first communication device that transmits transmission data containing user data and control data, and a second communication device that receives the transmission data from the first communication device. The second communication device includes a temporary storing unit that temporarily stores therein the received transmission data, and a space-insufficient-information transmitting unit that transmits, when an amount of the transmission data stored in the temporary storing unit exceeds a first threshold, space insufficient information indicating that available storage space of the temporary storing unit is insufficient to the first communication device.

Abstract: A computing system is disclosed that includes a memory controller in a processor socket normally reserved for a processor. A plurality of non-volatile memory modules may be plugged into memory sockets normally reserved for DRAM memory modules. The non-volatile memory modules may be accessed using a data communication protocol to access the non-volatile memory modules. The memory controller controls read and write accesses to the non-volatile memory modules. The memory sockets are coupled to the processor socket by printed circuit board traces. The data communication protocol to access the non-volatile memory modules is communicated over the printed circuit board traces and through the sockets normally used to access DRAM type memory modules.

Abstract: A memory controller that controls data transfer between a volatile memory and a non-volatile memory, wherein data being held in a plurality of volatile memories each having a refresh operation mode and a self-refresh operation mode is transferred to the non-volatile memory. When readout of data from at least one volatile memory has been finished, the volatile memory is shifted from the refresh operation mode to the self-refresh operation mode. Then, control is performed so as to return the volatile memory from the self-refresh operation mode depending on the progress of writing of data to the non-volatile memory.