Patents Examined by Diana C Vieira
-
Patent number: 10269759Abstract: A bump-on-trace (BOT) interconnection in a package and methods of making the BOT interconnection are provided. An embodiment BOT interconnection comprises a landing trace including a distal end, a conductive pillar extending at least to the distal end of the landing trace; and a solder feature electrically coupling the landing trace and the conductive pillar. In an embodiment, the conductive pillar overhangs the end surface of the landing trace. In another embodiment, the landing trace includes one or more recesses for trapping the solder feature after reflow. Therefore, a wetting area available to the solder feature is increased while permitting the bump pitch of the package to remain small.Type: GrantFiled: March 10, 2017Date of Patent: April 23, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yen-Liang Lin, Chen-Shien Chen, Tin-Hao Kuo
-
Patent number: 10205002Abstract: The present disclosure generally relate to methods of processing a substrate in an epitaxy chamber. The method includes exposing a substrate having one or more fins to a group IV-containing precursor and a surfactant containing antimony to form an epitaxial film over sidewalls of the one or more fin structures, wherein the surfactant containing antimony is introduced into the epitaxy chamber before epitaxial growth of the epitaxial film, and a molar ratio of the surfactant containing antimony to the group IV-containing precursor is about 0.0001 to about 10.Type: GrantFiled: January 27, 2017Date of Patent: February 12, 2019Assignee: APPLIED MATERIALS, INC.Inventors: Xinyu Bao, Chun Yan, Errol Antonio C. Sanchez, Hua Chung
-
Patent number: 10192899Abstract: A display includes a first substrate, a second substrate, a plurality of pixels and a photo-catalyst layer. The plurality of pixels are disposed between the first substrate and the second substrate. The photo-catalyst layer is disposed above a surface of the second substrate facing the first substrate or above a surface of the first substrate facing the second substrate. Manufacturing methods of a display are additionally disclosed.Type: GrantFiled: December 9, 2016Date of Patent: January 29, 2019Assignee: AU OPTRONICS CORPORATIONInventor: Shih-Hsing Hung
-
Patent number: 10186568Abstract: An organic light emitting display device includes a thin film transistor (TFT) including a gate electrode and a source electrode. An anode electrode is disposed on the TFT, and a cathode electrode disposed on an organic emission layer is connected to an auxiliary electrode which is disposed on a same layer on which the anode electrode is disposed. A signal pad disposed in a pad area of a substrate is disposed on a same layer on which the gate electrode is disposed in an active area of the substrate. A pad electrode disposed on the signal pad is connected to the signal pad through a contact hole.Type: GrantFiled: December 30, 2015Date of Patent: January 22, 2019Assignee: LG DISPLAY CO., LTD.Inventors: SeJune Kim, Joonsuk Lee, SoJung Lee, Jin-Hee Jang, Jonghyeok Im, JaeSung Lee
-
Patent number: 10170431Abstract: Disclosed herein is an electronic circuit package includes a substrate having a power supply pattern, a first electronic component mounted on a first region of a front surface of the substrate, a mold resin that covers the front surface of the substrate so as to embed the first electronic component therein and has a concave portion above the first region, a magnetic film selectively provided in the concave portion, and a first metal film that is connected to the power supply pattern and covers the mold resin.Type: GrantFiled: December 16, 2016Date of Patent: January 1, 2019Assignee: TDK CORPORATIONInventors: Kenichi Kawabata, Toshio Hayakawa, Toshiro Okubo
-
Patent number: 10153256Abstract: A micro-transfer printable electronic component includes one or more electronic components, such as integrated circuits or LEDs. Each electronic component has device electrical contacts for providing electrical power to the electronic component and a post side. A plurality of electrical conductors includes at least one electrical conductor electrically connected to each of the device electrical contacts. One or more electrically conductive connection posts protrude beyond the post side. Each connection post is electrically connected to at least one of the electrical conductors. Additional connection posts can form electrical jumpers that electrically connect electrical conductors on a destination substrate to which the printable electronic component is micro-transfer printed. The printable electronic component can be a full-color pixel in a display.Type: GrantFiled: December 9, 2016Date of Patent: December 11, 2018Assignee: X-Celeprint LimitedInventors: Ronald S. Cok, Christopher Bower, Matthew Meitl, Carl Prevatte, Jr.
-
Patent number: 10153257Abstract: A micro-printed display includes a display substrate. An array of row conductors, an array of column conductors, and a plurality of micro-pixels are disposed on the display substrate. Each micro-pixel is uniquely connected to a row and a column conductor and comprises a pixel substrate separate from the display substrate and the pixel substrate of any other micro-pixel. Pixel conductors are patterned on each pixel substrate and one or more LEDs are disposed on or over the pixel substrate. Each LED is electrically connected to one or more of the pixel conductors and has an LED substrate separate from any other LED substrate, the display substrate, and any pixel substrate. A pixel controller disposed on the pixel substrate can control the LEDs. The micro-pixel can be electrically connected to the display substrate with connection posts. Redundant or replacement LEDs or micro-pixels can be provided on the pixel or display substrate.Type: GrantFiled: March 10, 2017Date of Patent: December 11, 2018Assignee: X-Celeprint LimitedInventors: Ronald S. Cok, Christopher Andrew Bower, Matthew Meitl, Carl Ray Prevatte, Jr., Salvatore Bonafede, Robert R. Rotzoll
-
Patent number: 10141411Abstract: A semiconductor device includes a semiconductor substrate of silicon carbide, and a temperature sensor portion. The semiconductor substrate includes a portion in which an n-type drift region and a p-type body region are laminated. The temperature sensor portion is disposed in the semiconductor substrate and is separated from the drift region by the body region. The temperature sensor portion includes an n-type cathode region being in contact with the body region, and a p-type anode region separated from the body region by the cathode region.Type: GrantFiled: February 17, 2017Date of Patent: November 27, 2018Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATIONInventors: Atsushi Onogi, Toru Onishi, Shuhei Mitani, Yusuke Yamashita, Katsuhiro Kutsuki
-
Patent number: 10062700Abstract: A manufacturing method of a semiconductor storage device includes forming a plurality of bit line structures on a semiconductor substrate and forming a plurality of storage node contacts disposed between the bit line structures. The method of forming the storage node contacts includes forming a plurality of conductive patterns on the semiconductor substrate followed by performing an etching back process to the conductive patterns for decreasing a thickness of the conductive patterns. The manufacturing method further includes forming a plurality of isolation patterns between the conductive patterns, wherein the isolation patterns are formed after forming the plurality of conductive patterns and before the etching back process. According to the present invention, the storage node contacts are formed by first forming the conductive patterns and then forming the isolation patterns between the conductive patterns, so as to simplify manufacturing process and increase process yield.Type: GrantFiled: March 14, 2017Date of Patent: August 28, 2018Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Feng-Yi Chang, Fu-Che Lee, Chien-Cheng Tsai, Feng-Ming Huang, Hsien-Shih Chu
-
Patent number: 10026825Abstract: A semiconductor may include a semiconductor substrate including a first region and a second region disposed at opposite sides of the first region, a first trench formed in the first region, a buffer layer filling a portion of the first trench, a first semiconductor layer formed on the buffer layer, a second semiconductor layer forming a hetero-junction with the first semiconductor layer on the first semiconductor layer of the first region and a gate electrode formed on the second semiconductor layer of the first region.Type: GrantFiled: December 9, 2016Date of Patent: July 17, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Jae Hoon Lee
-
Patent number: 9972710Abstract: A field effect transistor includes a semiconductor stack including a channel provided on a border between a first nitride semiconductor and a second nitride semiconductor provided on the first nitride semiconductor in a stacking direction. A source electrode, a gate electrode, and a drain electrode are disposed on the semiconductor stack. The gate electrode is disposed between the source electrode and the drain electrode. At least one hole is provided to pass through the channel from the first nitride semiconductor to the second nitride semiconductor to provide channel paths from the gate electrode to the drain electrode. A minimum distance of the channel paths is longer than a minimum distance between the gate electrode and drain electrode viewed in the stacking direction. The insulating member is filled in the at least one hole and has a breakdown field strength higher than a breakdown field strength of the semiconductor stack.Type: GrantFiled: December 16, 2016Date of Patent: May 15, 2018Assignee: NICHIA CORPORATIONInventor: Masashi Tanimoto
-
Patent number: 9941244Abstract: In accordance with a method embodiment includes providing a die having a contact pad on a top surface and forming a conductive protective layer over the die and covering the contact pad. A molding compound is formed over the die and the conductive protective layer. The conductive protective layer is exposed using a laser drilling process. A redistribution layer (RDL) is formed over the die. The RDL is electrically connected to the contact pad through the conductive protective layer.Type: GrantFiled: December 9, 2013Date of Patent: April 10, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chin-Chuan Chang, Tsei-Chung Fu, Jing-Cheng Lin
-
Patent number: 9917198Abstract: The present disclosure provides an array substrate, a manufacturing method thereof and a display device. The array substrate includes an active layer, a gate insulating layer and a gate electrode layer formed sequentially on a base substrate. The active layer includes a first heavily-doped region, a first lightly-doped region, a first non-doped region, a second lightly-doped region, a second non-doped region, a third lightly-doped region and a second heavily-doped region which are sequentially arranged in a horizontal direction.Type: GrantFiled: February 12, 2015Date of Patent: March 13, 2018Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventor: Zhenyu Xie
-
Patent number: 9876004Abstract: A semiconductor component including a short-circuit structure. One embodiment provides a semiconductor component having a semiconductor body composed of doped semiconductor material. The semiconductor body includes a first zone of a first conduction type and a second zone of a second conduction type, complementary to the first conduction type, the second zone adjoining the first zone. The first zone and the second zone are coupled to an electrically highly conductive layer. A connection zone of the second conduction type is arranged between the second zone and the electrically highly conductive layer.Type: GrantFiled: February 5, 2016Date of Patent: January 23, 2018Assignee: Infineon Technologies AGInventors: Hans-Joachim Schulze, Franz-Josef Niedernostheide, Uwe Kellner-Werdehausen, Reiner Barthelmess
-
Patent number: 9633920Abstract: The present disclosure relates to a structure and method of forming a low damage passivation layer for III-V HEMT devices. In some embodiments, the structure has a bulk buffer layer disposed over a substrate and a device layer of III-V material disposed over the bulk buffer layer. A source region, a drain region and a gate region are disposed above the device layer. The gate region comprises a gate electrode overlying a gate separation layer. A bulk passivation layer is arranged over the device layer, and an interfacial layer of III-V material is disposed between the bulk passivation layer and the device layer in such a way that the source region, the drain region and the gate region extend through the bulk passivation layer and the interfacial layer, to abut the device layer.Type: GrantFiled: February 12, 2015Date of Patent: April 25, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Han-Chin Chiu, Cheng-Yuan Tsai, Ming-Wei Tsai, Yao-Wen Chang, Wen-Yuan Hsieh
-
Patent number: 9627509Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a substrate with an active pattern, a gate electrode provided at the active pattern, and a gate capping structure disposed above the gate electrode. The gate capping structure may include two or more gate capping patterns with different properties from each other, and the use of the gate capping structure makes it possible to form contact plugs in a self-aligned manner and improve operational speed and characteristics of the semiconductor device.Type: GrantFiled: July 17, 2015Date of Patent: April 18, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyungbum Koo, Wandon Kim, Sangjin Hyun, Shinhye Kim, TaekSoo Jeon, Byung-Suk Jung
-
Patent number: 9620731Abstract: A thin film transistor according to the present disclosure including: a gate electrode above a substrate; a gate insulating layer covering the gate electrode; a semiconductor layer above the gate insulating layer; and a source electrode and a drain electrode which are above the gate insulating layer, and electrically connected to the semiconductor layer, in which the gate insulating layer includes a first area and a second area, the first area being above the gate electrode, the second area being different from an area above the gate electrode, and made of a same substance as the first area, and the first area has a higher density than a density of the second area.Type: GrantFiled: September 24, 2013Date of Patent: April 11, 2017Assignee: PANASONIC COPRORATIONInventors: Takaaki Ukeda, Akihito Miyamoto, Norishige Nanai
-
Patent number: 9620592Abstract: A semiconductor device includes a substrate and a p-doped layer including a doped III-V material on the substrate. An n-doped layer is formed on the p-doped layer, the n-doped layer including a doped III-V material. A contact interface layer is formed on the n-doped layer. The contact interface layer includes a II-VI material. A contact metal is formed on the contact interface layer to form an electronic device.Type: GrantFiled: February 12, 2015Date of Patent: April 11, 2017Assignee: International Business Machines CorporationInventors: Joel P. de Souza, Keith E. Fogel, Jeehwan Kim, Siegfried L. Maurer, Devendra K. Sadana
-
Patent number: 9601387Abstract: Methods of forming a PFET dielectric cap with varying concentrations of H2 reactive gas and the resulting devices are disclosed. Embodiments include forming p-type and n-type metal gate stacks, each surrounded by SiN spacers; forming an ILD surrounding the SiN spacers; planarizing the ILD, the metal gate stacks, and the SiN spacers; determining at least one desired threshold voltage for the p-type metal gate stack; forming a first cavity in the p-type metal gate stack for each desired threshold voltage and a second cavity in the n-type metal gate stack; selecting a first nitride layer for each first cavity, the first nitride layer for each cavity having a concentration of hydrogen reactive gas based on the desired threshold voltage associated with the cavity; forming the first nitride layers in the respective first cavities; and forming a second nitride layer, with a hydrogen rich reactive gas, in the second cavity.Type: GrantFiled: January 3, 2014Date of Patent: March 21, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Xiuyu Harry Cai, Chanro Park, Hoon Kim
-
Patent number: 9583478Abstract: A lateral power MOSFET structure is disclosed. In some embodiments, a semiconductor device comprises substantially concentric source, channel, and drain regions; a metal layer at least in part comprising a drain plane disposed over the source, channel, and drain regions; and a metal layer at least in part comprising a source plane disposed over the source, channel, and drain regions.Type: GrantFiled: April 18, 2011Date of Patent: February 28, 2017Assignee: Silego Technology, Inc.Inventor: Marcelo A. Martinez