Abstract: An image sensor pixel includes a semiconductor layer, a photosensitive region to accumulate photo-generated charge, a floating node, a trench, and an entrenched transfer gate. The photosensitive region and the trench are disposed within the semiconductor layer. The trench extends into the semiconductor layer between the photosensitive region and the floating node and the entrenched transfer gate is disposed within the trench to control transfer of the photo-generated charge from the photosensitive region to the floating node.

Abstract: A display panel having a plurality of pixel units arranged in an array includes an array substrate and a color filter substrate which are arranged opposite to each other. The array substrate includes a first electrode, and multiple second electrodes arranged corresponding to the respective pixel units, the first electrode and second electrodes are insulated from each other by an insulation layer; and the color filter substrate includes multiple black matrixes and multiple color resists arranged corresponding to the respective pixel units. The array substrate further includes multiple third electrodes arranged in boundary areas between two adjacent pixel units and opposite to the black matrixes. The third electrodes and the first electrode are disposed in different layers and have a same potential.

Abstract: A contact structure includes a first contact formed in a first dielectric layer connecting to the source/drain region of a MOS transistor, and a second contact formed in a second dielectric layer connecting to a gate region of a MOS transistor or to a first contact. A butted contact structure abutting a source/drain region and a gate electrode includes a first contact formed in a first dielectric layer connecting to the source/drain region of a MOS transistor, and a second contact formed in a second dielectric layer with one end resting on the gate electrode and the other end in contact with the first contact.

Abstract: A conductive structure is formed in a last metal layer of an integrated circuit. Passivation material is patterned over a portion of the conductive structure. A first trench is patterned around a selected portion of the passivation material. The selected portion represents a bond region of a wire bond to be formed above the passivation material. A portion of the passivation material completely covers a bottom of the trench. A layer of conductive material is conformally deposited over the passivation material. The conformal depositing resulting in a second trench forming in the conductive material over the first trench in the passivation material. The second trench is positioned to contain at least a portion of a splash of the conductive material when the wire bond is subsequently formed.

Abstract: At least one via level dielectric layer and at least one line level dielectric layer are sequentially formed over an array of device structures. Conductive line structures are formed within the at least one line level dielectric layer. A mask layer is applied over the conductive line structures, and is lithographically patterned to form opening therein. Portions of the conductive line structures are removed from underneath the openings in the patterned mask layer to form via cavities. The via cavities are vertically extended through the at least one via level dielectric layer employing a combination of the mask layer and the at least one line level dielectric layer as an etch mask. At least one conductive material can be deposited in the via cavities to form conductive via structures, which, in conjunction with the conductive line structures, constitute integrated line and via structures.

Abstract: The present invention is a method and an apparatus for optical modulation, for example for use in optical communications links. In one embodiment, an apparatus for optical modulation includes a first silicon layer having one or more trenches formed therein, a dielectric layer lining the first silicon layer, and a second silicon layer disposed on the dielectric layer and filling the trenches.

Abstract: A method of forming a semiconductor structure having a metal gate. Firstly, a semiconductor substrate is provided. Subsequently, at least a gate structure is formed on the semiconductor substrate. Afterwards, a spacer structure is formed to surround the gate structure. Then, an interlayer dielectric is formed. Afterwards, a planarization process is performed for the interlayer dielectric. Then, a portion of the sacrificial layer is removed to form an initial etching depth, such that an opening is formed to expose a portion of the spacer structure. The portion of the spacer structure exposed to the opening is removed so as to broaden the opening. Afterwards, remove the sacrificial layer completely via the opening. Finally, a gate conductive layer is formed to fill the opening.

Abstract: A semiconductor die has active circuits formed on its active surface. Contact pads are formed on the active surface of the semiconductor die and coupled to the active circuits. A die extension region is formed around a periphery of the semiconductor die. Conductive THVs are formed in the die extension region. A wafer level conductive plane or ring is formed on a center area of the active surface. The conductive plane or ring is connected to a first contact pad to provide a first power supply potential to the active circuits, and is electrically connected to a first conductive THV. A conductive ring is formed partially around a perimeter of the conductive plane or ring and connected to a second contact pad for providing a second power supply potential to the active circuits. The conductive ring is electrically connected to a second THV.

Abstract: A trenched semiconductor power device includes a trenched gate insulated by a gate insulation layer and surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a semiconductor substrate. The source region surrounding the trenched gate includes a metal of low barrier height to function as a Schottky source and that may include a PtSi, ErSi layer and may further be a metal silicide layer having the low barrier height. A top oxide layer is disposed under a silicon nitride spacer on top of the trenched gate for insulating the trenched gate from the source region. A source contact disposed in a trench opened into the body region for contacting a body-contact dopant region and covering with a conductive metal layer such as a Ti/TiN layer.

Abstract: The present invention provides a semiconductor structure, including a substrate, having a dielectric layer disposed thereon, a first device region and a second device region defined thereon, at least one first trench disposed in the substrate within the first device region, at least one second trench and at least one third trench disposed in the substrate within the second device region, a work function layer, disposed in the second trench and the third trench, wherein the work function layer partially covers the sidewall of the second trench, and entirely covers the sidewall of the third trench, and a first material layer, disposed in the second trench and the third trench, wherein the first material layer covers the work function layer disposed on partial sidewall of the second trench, and entirely covers the work function layer disposed on the sidewall of the third trench.

Abstract: A semiconductor component including a short-circuit structure. One embodiment provides a semiconductor component having a semiconductor body composed of doped semiconductor material. The semiconductor body includes a first zone of a first conduction type and a second zone of a second conduction type, complementary to the first conduction type, the second zone adjoining the first zone. The first zone and the second zone are coupled to an electrically highly conductive layer. A connection zone of the second conduction type is arranged between the second zone and the electrically highly conductive layer.

Abstract: An integrated circuit memory device, including a memory circuit and a peripheral circuit, is described which is suitable for low cost manufacturing. The memory circuit and peripheral circuit for the device are implemented in different layers of a stacked structure. The memory circuit layer and the peripheral circuit layer include complementary interconnect surfaces, which upon mating together establish the electrical interconnection between the memory circuit and the peripheral circuit. The memory circuit layer and the peripheral circuit layer can be formed separately using different processes on different substrates in different fabrication lines. This enables the use of independent fabrication process technologies, one arranged for the memory array, and another arranged for the supporting peripheral circuit. The separate circuitry can then be stacked and bonded together.

Abstract: Methods, IC and related transistors using capping layer with high-k/metal gate stacks are disclosed. In one embodiment, the IC includes a first type transistor having a gate electrode including a first metal, a second metal and a first dielectric layer, the first dielectric layer including oxygen; a second type transistor separated from the first type transistor by an isolation region, the second type transistor having a gate electrode including the second metal having a work function appropriate for the second type transistor and the first dielectric layer; and wherein the gate electrode of the first type transistor includes a rare earth metal between the first metal and the second metal and the gate electrode of the second type transistor includes a second dielectric layer made of an oxide of the rare earth metal.

Abstract: An integrated circuit arrangement is provided, including a transistor including a gate region; and a wavelength conversion element, wherein the wavelength conversion element may include the same material or same materials as the gate region of the transistor.

Abstract: Methods, devices, and systems are provided for a select device that can include a semiconductive stack of at least one semiconductive material formed on a first electrode, where the semiconductive stack can have a thickness of about 700 angstroms (?) or less. Each of the at least one semiconductive material can have an associated band gap of about 4 electron volts (eV) or less and a second electrode can be formed on the semiconductive stack.

Abstract: The present invention provides antifuse structures having an integrated heating element and methods of programming the same, the antifuse structures comprising first and second conductors and a dielectric layer formed between the conductors, where one or both of the conductors functions as both a conventional antifuse conductor and as a heating element for directly heating the antifuse dielectric layer during programming.

Abstract: A light emitting device having a light extraction structure, which is capable of achieving an enhancement in light extraction efficiency and reliability, and a method for manufacturing the same. The light emitting device includes a semiconductor layer having a multi-layered structure including a light emission layer; and a light extraction structure formed on the semiconductor layer in a pattern having unit structures. Further, the wall of each of the unit structures is sloped at an angle of ?45° to +45° from a virtual vertical line being parallel to a main light emitting direction of the light emitting device.

Abstract: A tunable protection system including forming a tunable trigger device providing an adjustable protection activation level, forming a circuit protection device providing protection for integrated circuits, and electrically connecting the tunable trigger device and the circuit protection device to an input/output pad.

Abstract: A lighting apparatus having wavelength-converting materials formed in a carrier layer is disclosed. In one embodiment, the lighting apparatus has a light source attached to a substrate that is assembled in a housing. The light source is configured to emit a substantially narrow band light that is transformed into broad-spectrum white light by the wavelength-converting materials positioned on the carrier layer. The wavelength-converting materials and the carrier layer are distanced away from the light source, such that the carrier layer is thermally isolated from the light source.

Abstract: A semiconductor power device supported on a semiconductor substrate that includes a plurality of transistor cells, each cell has a source and a drain region disposed on opposite sides of a gate region in the semiconductor substrate. A gate electrode is formed as an electrode layer on top of the gate region for controlling an electric current transmitted between the source and the drain regions. The gate electrode layer disposed on top of the semiconductor substrate is patterned into a wave-like shaped stripes for substantially increasing an electric current conduction area between the source and drain regions across the gate.