Patents Examined by Diana C Vieira
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Patent number: 9136291Abstract: A solid-state imaging device includes an imaging element, an external terminal, an insulating film, a penetration electrode, a first insulating interlayer, a first electrode, and a first contact plug. The imaging element is formed on a first main surface of a semiconductor substrate. The external terminal is formed on a second main surface facing the first main surface of the substrate. The insulating film is formed in a through-hole formed in the substrate. The penetration electrode is formed on the insulating film in the through-hole and electrically connected to the external terminal. The first insulating interlayer is formed on the first main surface of the substrate and the penetration electrode. The first electrode is formed on the first insulating interlayer. The first contact plug is formed in the first insulating interlayer between the penetration electrode and the first electrode to electrically connect the penetration electrode and the first electrode.Type: GrantFiled: June 7, 2012Date of Patent: September 15, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Mariko Saito, Ikuko Inoue
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Patent number: 9135924Abstract: There is provided a noise suppressing device, for suppressing a noise component contained in a sound, including: at least two sound receiving parts receiving sounds from a plurality of directions containing a sound from a direction of a given sound source and converting the sounds to digital sound signals in a time domain, respectively; an estimating part acquiring both direction information on a direction of the given sound source and distance information on a distance from the given sound source based upon the digital sound signals converted by the sound receiving parts, and estimating a component value of a noise component contained in the signal by use of the direction information and the distance information; and a controlling part acquiring a control value of a suppression amount for controlling a range of a direction of the digital sound signals.Type: GrantFiled: April 30, 2009Date of Patent: September 15, 2015Assignee: FUJITSU LIMITEDInventors: Shoji Hayakawa, Naoshi Matsuo
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Patent number: 9113240Abstract: Signal processing solutions take advantage of microphones located on different devices and improve the quality of transmitted voice signals in a communication system. With usage of various devices such as Bluetooth headsets, wired headsets and the like in conjunction with mobile handsets, multiple microphones located on different devices are exploited for improving performance and/or voice quality in a communication system. Audio signals are recorded by microphones on different devices and processed to produce various benefits, such as improved voice quality, background noise reduction, voice activity detection and the like.Type: GrantFiled: March 16, 2009Date of Patent: August 18, 2015Assignee: QUALCOMM IncorporatedInventors: Dinesh Ramakrishnan, Song Wang
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Patent number: 9098736Abstract: An improved diagnostic resolution of digital slide images is obtained by scanning a first digital slide image at diagnostic resolution that is then deconvolved into separate images with one stain per image. The single stain images are then enhanced with image adjustments and/or processed with image analysis algorithms. The resulting single image data sets from the image analysis algorithms can then be stored. Additionally, the resulting enhanced single images can be recombined into a second digital slide image at diagnostic resolution that is also enhanced.Type: GrantFiled: September 19, 2008Date of Patent: August 4, 2015Assignee: LEICA BIOSYSTEMS IMAGING, INC.Inventors: Dirk G. Soenksen, Cindy Perz
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Patent number: 9099387Abstract: A semiconductor device includes an n-conductive type semiconductor substrate having a main side and a rear side, a p-conductive type layer arranged over the main side of the substrate, a main side n-conductive type region arranged in the p-conductive type layer, a rear side n-conductive type layer arranged over the rear side of the substrate, a first trench which reaches the substrate and penetrates the main side n-conductive type region and the p-conductive type layer, a second trench which reaches an inside of the p-conductive type layer, a second electrode layer, which is embedded in the second trench and connected to the p-conductive type layer. Hereby, the semiconductor device, in which the recovery property of a diode cell can be improved without damaging the property of a MOS transistor cell or an IGBT cell and the surge withstand property does not deteriorate, can be obtained.Type: GrantFiled: June 28, 2011Date of Patent: August 4, 2015Assignee: DENSO CORPORATIONInventors: Yukio Tsuzuki, Makoto Asai
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Patent number: 9087925Abstract: Semiconductor structures and methods of forming semiconductor structures, and more particularly to structures and methods of forming SiGe and/or SiGeC buried layers for SOI/SiGe devices. An integrated structure includes discontinuous, buried layers having alternating Si and SiGe or SiGeC regions. The structure further includes isolation structures at an interface between the Si and SiGe or SiGeC regions to reduce defects between the alternating regions. Devices are associated with the Si and SiGe or SiGeC regions.Type: GrantFiled: June 1, 2011Date of Patent: July 21, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Xuefeng Liu, Robert M. Rassel, Steven H. Voldman
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Patent number: 9059034Abstract: An EEPROM includes: a semiconductor layer of a first conductive type; and a first insulating film formed on the semiconductor layer. First through fifth impurity regions are formed in top layer portions of the semiconductor layer. On the first insulating film, a select gate, and first and second floating gates are respectively disposed opposite a region between the first impurity region and the second impurity region, a region between the second impurity region and the third impurity region, and a region between the third impurity region and the fourth impurity region. In the first insulating film, first and second tunnel windows are respectively formed at portions in contact with the first and second floating gates. A sixth impurity region of the second conductive type, which is connected to the second impurity region, is formed in the top layer portion of the semiconductor layer that opposes the second tunnel window.Type: GrantFiled: August 24, 2011Date of Patent: June 16, 2015Assignee: ROHM CO., LTD.Inventor: Yushi Sekiguchi
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Patent number: 9048254Abstract: A method of forming a semiconductor structure having a metal gate. Firstly, a semiconductor substrate is provided. Subsequently, at least a gate structure is formed on the semiconductor substrate. Afterwards, a spacer structure is formed to surround the gate structure. Then, an interlayer dielectric is formed. Afterwards, a planarization process is performed for the interlayer dielectric. Then, a portion of the sacrificial layer is removed to form an initial etching depth, such that an opening is formed to expose a portion of the spacer structure. The portion of the spacer structure exposed to the opening is removed so as to broaden the opening. Afterwards, remove the sacrificial layer completely via the opening. Finally, a gate conductive layer is formed to fill the opening.Type: GrantFiled: December 2, 2009Date of Patent: June 2, 2015Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yi-Wei Chen, Nien-Ting Ho, Chien-Chung Huang, Chin-Fu Lin
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Patent number: 9000502Abstract: Methods, devices, and systems are provided for a select device that can include a semiconductive stack of at least one semiconductive material formed on a first electrode, where the semiconductive stack can have a thickness of about 700 angstroms (?) or less. Each of the at least one semiconductive material can have an associated band gap of about 4 electron volts (eV) or less and a second electrode can be formed on the semiconductive stack.Type: GrantFiled: April 19, 2011Date of Patent: April 7, 2015Assignee: Micron Technology, Inc.Inventors: D. V. Nirmal Ramaswamy, Gurtej S. Sandhu
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Lighting device having luminescent material between a reflective cup and a solid state light emitter
Patent number: 8994045Abstract: A lighting device comprising a light emitter chip, a reflective cup and a lumiphor positioned between the chip and the cup. Also, a lighting device comprising a light emitter chip, a wire bonded to a first surface of the chip and a lumiphor which faces a second surface of the chip. Also, a lighting device comprising a light emitter chip, and a lumiphor, a first surface of the chip facing a first region of the lumiphor, a second surface of the chip facing a second region of the lumiphor. Also, a lighting device comprising a light emitter chip and first and second lumiphors, a first surface of the chip facing the second lumiphor, a second surface of the chip facing the first lumiphor. Also, methods of making lighting devices.Type: GrantFiled: October 11, 2007Date of Patent: March 31, 2015Assignee: Cree, Inc.Inventor: Gerald H. Negley -
Patent number: 8965001Abstract: A microphone rubber apparatus mounted on an SMD microphone prepared on a printed circuit board to protect the SMD microphone from an external physical impact and the like in a portable communication device such as a portable terminal and a Personal Digital Assistant (PDA). The microphone rubber apparatus includes a microphone holder portion formed to engage with and wrap up a microphone, a connection portion protruding to one side of the microphone holder portion and delivering a transmission sound to the microphone through an inside thereof, and at least one shock absorbing portion deformably formed around the connection portion to ease an impact caused by an external force. Thus, the shock absorbing portion having a wrinkled shape can be deformed no matter in which direction an impact is applied to the portable communication device, thereby easing the impact and preventing the microphone rubber from being detached from the microphone due to the external impact or during a distribution test.Type: GrantFiled: May 22, 2009Date of Patent: February 24, 2015Assignee: Samsung Electronics Co., Ltd.Inventor: Boo-Hyun Kang
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Patent number: 8963169Abstract: Photonic devices monolithically integrated with CMOS are disclosed, including sub-100 nm CMOS, with active layers comprising acceleration regions, light emission and absorption layers, and optional energy filtering regions. Light emission or absorption is controlled by an applied voltage to deposited films on a pre-defined CMOS active area of a substrate, such as bulk Si, bulk Ge, Thick-Film SOI, Thin-Film SOI, Thin-Film GOI.Type: GrantFiled: July 28, 2005Date of Patent: February 24, 2015Assignee: Quantum Semiconductor LLCInventor: Carlos J. R. P. Augusto
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Patent number: 8952412Abstract: A method for manufacturing a solid-state imaging device. A solid-state image sensor is mounted on the semiconductor package support and electrically connected to first terminals and second terminals by bonding wires. The second terminals to which the bonding wires are connected are sealed with a sealing member. The optically-transparent member is thereafter disposed on the support member and the sealing member. The sealing member is cured to fix the optically transparent member.Type: GrantFiled: September 8, 2009Date of Patent: February 10, 2015Assignee: Sony CorporationInventor: Noboru Kawabata
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Patent number: 8952547Abstract: A contact structure includes a first contact formed in a first dielectric layer connecting to the source/drain region of a MOS transistor, and a second contact formed in a second dielectric layer connecting to a gate region of a MOS transistor or to a first contact. A butted contact structure abutting a source/drain region and a gate electrode includes a first contact formed in a first dielectric layer connecting to the source/drain region of a MOS transistor, and a second contact formed in a second dielectric layer with one end resting on the gate electrode and the other end in contact with the first contact.Type: GrantFiled: July 9, 2007Date of Patent: February 10, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Jhon-Jhy Liaw
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Patent number: 8946878Abstract: An integrated circuit package-in-package system is provided including mounting first integrated circuits stacked in a first offset configuration over a die-attach paddle having a first edge and a second edge, opposing the first edge; connecting the first integrated circuits and a second edge lead adjacent the second edge; mounting second integrated circuits stacked in a second offset configuration, below and to the die-attach paddle; connecting the second integrated circuits and a first edge lead adjacent to the first edge; and encapsulating the first integrated circuits, second integrated circuits, and the die-attach paddle, with the first edge lead and the second edge lead partially exposed.Type: GrantFiled: December 6, 2007Date of Patent: February 3, 2015Assignee: STATS ChipPAC Ltd.Inventors: Chee Keong Chin, Jae Hak Yee, Yu Feng Feng, Frederick Cruz Santos
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Patent number: 8946803Abstract: Floating gates of a floating gate memory array have an inverted-T shape in both the bit line direction and the word line direction. Floating gates are formed using an etch stop layer that separates two polysilicon layers that form floating gates. Word lines extend over floating gates in one example, and word lines extend between floating gates in another example.Type: GrantFiled: December 6, 2007Date of Patent: February 3, 2015Assignee: SanDisk Technologies Inc.Inventors: George Matamis, Henry Chien, Vinod Robert Purayath, Takashi Whitney Orimoto, James Kai
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Patent number: 8927995Abstract: A thin film transistor includes a semiconductor pattern disposed on a substrate and a semiconductor pattern portion with a conductive or nonconductive characteristic, and a anti-diffusion portion on a side of the semiconductor pattern portion to prevent metal ions from being diffused along the semiconductor pattern portion. A first insulating layer covers the semiconductor pattern and has a first contact hole exposing a first region of the semiconductor pattern portion and a second contact hole exposing a second region of the semiconductor pattern portion. A gate electrode is disposed on the first insulating layer. A second insulating layer covers the gate electrode and has a third contact hole exposing the first region and a fourth contact hole exposing the second region. A source electrode is formed on the second insulating layer and connected to the first region, and a drain electrode is formed on the second insulating layer and connected to the second region.Type: GrantFiled: October 16, 2006Date of Patent: January 6, 2015Assignee: LG Display Co., Ltd.Inventors: Hong Koo Lee, Sang Hoon Jung
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Patent number: 8923530Abstract: A method is disclosed for acoustic feedback attenuation at a telecommunications terminal. A speakerphone equipped with a loudspeaker and two microphones is featured. Signals from the two microphones are subjected to a calibration stage and then to a runtime stage. The purpose of the calibration stage is to match the microphones to each other by advantageously using both magnitude and phase equalization across the frequency spectrum of the microphones. During the runtime stage, the microphones monitor the ambient sounds received from sound sources, such as the speakerphone's users and the loudspeaker itself, during a conference call. The speakerphone applies the generated set of filter coefficients to the optimized microphone's signals. By combining the signal from the reference microphone with the filtered signal from the optimized microphone, the speakerphone is able to attenuate the sounds from the loudspeaker that would otherwise be transmitted back to other conference call participants.Type: GrantFiled: April 10, 2009Date of Patent: December 30, 2014Assignee: Avaya Inc.Inventors: Eric John Diethorn, Heinz Teutsch
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Patent number: 8907405Abstract: Semiconductor structures with dual trench regions and methods of manufacturing the semiconductor structures are provided herein. The method includes forming a gate structure on an active region and high-k dielectric material formed in one or more trenches adjacent to the active region. The method further includes forming a sacrificial material over the active region and portions of the high-k dielectric material adjacent sidewalls of the active region. The method further includes removing unprotected portions of the high-k dielectric material, leaving behind a liner of high-k dielectric material on the sidewalls of the active region. The method further includes removing the sacrificial material and forming a raised source and drain region adjacent to sidewalls of the gate structure.Type: GrantFiled: April 18, 2011Date of Patent: December 9, 2014Assignee: International Business Machines CorporationInventors: Reinaldo A. Vega, Hongwen Yan
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Patent number: 8884410Abstract: A method for manufacturing a microelectronic package (1) comprises the steps of providing at least two members (10, 11, 16) comprising electrically conductive material; providing a microelectronic device (15); placing the electrically conductive members (10, 11, 16) and the microelectronic device (15) in predetermined positions with respect to each other, and establishing electrical connections between each of the electrically conductive members (10, 11, 16) and the microelectronic device (15); and providing a non-conductive material for encapsulating the microelectronic device (15) and a portion of the electrically conductive members (10, 11, 16) connected thereto. The electrically conductive members (10, 11, 16) are intended to be used for realizing contact of the microelectronic device (15) arranged inside the package (1) to the external world.Type: GrantFiled: October 16, 2009Date of Patent: November 11, 2014Assignee: NXP B.V.Inventors: Peter Wilhelmus Maria Van De Water, Paulus Martinus Catharina Hesen, Roelf Anco Jacob Groenhuis