Abstract: An organic light-emitting display apparatus is disclosed. In one embodiment, the display apparatus includes i) a substrate and ii) an organic light-emitting device formed on the substrate, the organic light-emitting device including a stack structure including a first electrode, an organic light-emitting layer, and a second electrode. The apparatus may further include a sealing layer formed on the substrate so as to cover the organic light-emitting device, the sealing layer including an inorganic layer and a porous layer interposed between the sealing layer and the organic light-emitting device. One embodiment can reduce a stress due to a sealing inorganic layer so as to maintain characteristics for a long time in a severe environment and not affect an organic light-emitting device.

Abstract: A leadless package for semiconductor elements has at least two semiconductor elements which are situated on a connection region of a lead frame of the leadless package in such a way that when deformations of the semiconductor elements occur, the deformations of the semiconductor elements compensate one another.

Abstract: A description is given of a device comprising a first semiconductor chip, a molding compound layer embedding the first semiconductor chip, a first electrically conductive layer applied to the molding compound layer, a through hole arranged in the molding compound layer, and a solder material filling the through hole.

Abstract: A MOS transistor suppressing a short channel effect includes a substrate, a first diffusion region and a second diffusion region separated from each other by a channel region in an upper portion of the substrate, a gate insulating layer including a first gate insulating layer disposed on a surface of the substrate in the channel region and a second gate insulating layer having a specified depth from the surface of the substrate to be disposed between the first diffusion region and the channel region, and a gate electrode disposed on the first gate insulating layer.

Abstract: A leadless package and method for manufacturing silicon based leadless QFN/SON compatible packages are described. In addition the package allows for hermetic sealing of devices while maintaining electrical and optical access. Micro-vias with feed-through metallization through a silicon structure facilitates a surface mount technology-compatible silicon package with bottom SMT pads and top surface device integration. Sloped edges on the SMT side enable solder filleting for post solder inspection. Hermetic seal can be attained for example using anodic bonding of a glass lid or using metal soldering. Metal soldering enables the use of solder bumps to provide electrical connections for the package to the lid with integrated device functionality used for sealing. Hermetically sealed silicon packages eliminates the need for an extra packaging layer required in plastic packages and provides a standard interface for enclosing one or more discrete devices.

Abstract: An partially depleted Dieler LDMOSFET transistor (100) is provided which includes a substrate (150), a drift region (110) surrounding a drain region (128), a first well region (107) surrounding source region (127), a well buffer region (106) separating the drift region and first well region to at least partly define a first channel region, a gate electrode (118) formed over the first channel region having a source-side gate edge aligned with the first well region (107), an LDD extension region (120) extending from the source region to the channel region, and a dielectric RESURF drain extension structure (161) formed at the drain of the gate electrode (118) using the plurality of STI stripes (114).

Abstract: A flat panel display with a black matrix and a fabrication method of the same. The flat panel display has an insulating substrate at the upper part of which a pixel electrode is equipped; an opaque conductive film formed on the front surface of the insulating substrate except at the pixel electrode; an insulating film equipped with a contact hole exposing a portion of the opaque conductive film; and a thin film transistor equipped with a gate electrode, and conductive patterns for source/drain electrodes connected to the opaque conductive film through the contact hole.

Abstract: A semiconductor device and method for producing such a device is disclosed. One embodiment provides a semiconductor functional wafer having a first and second main surface. Component production processes are performed for producing a component functional region at the first main surface, wherein the component production processes produce an end state that is stable up to at least a first temperature. A carrier substrate is fitted to the first main surface. Access openings are produced to the first main surface. At least one further component production process is performed for producing patterned component functional regions at the first main surface of the functional wafer in the access openings. The end state produced in this process is stable up to a second temperature, which is less than the first temperature.

Abstract: A semiconductor structure and a fabricating method thereof are provided. The fabricating method includes forming a gate, a source, and a drain on a substrate and forming an oxide semiconductor material between the gate and the source and drain. The oxide semiconductor material is formed by performing a deposition process, and nitrogen gas is introduced before the deposition process is completely performed, so as to form oxide semiconductor nitride on the oxide semiconductor material.

Abstract: A pixel structure and a manufacturing method thereof are provided. In the pixel structure, an electrode of a storage capacitor is formed when an active layer is formed, and the electrode and the active layer are made of the same material. The material of the electrode and the active layer can be an oxide semiconductor with high transmittance. Therefore, a stable display frame of the pixel structure can be provided by the storage capacitor, an aperture ratio of the pixel structure can be improved, and power consumption can be further reduced.

Abstract: One close loop system and method for electrophoretic deposition (EPD) of phosphor material on light emitting diodes (LEDs). The system comprises a deposition chamber sealed from ambient air. A mixture of phosphor material and solution is provided to the chamber with the mixture also being sealed from ambient air. A carrier holds a batch of LEDs in the chamber with the mixture contacting the areas of the LEDs for phosphor deposition. A voltage supply applies a voltage to the LEDs and the mixture to cause the phosphor material to deposit on the LEDs at the mixture contacting areas.

Abstract: A device and method processing microphone signals from at least two microphones is presented. A first beamformer processes the signals from the microphones and provides a first beamformed signal. A power estimator processes the signals from the microphones and the first beamformed signal from the first beamformer in order to generate, in frequency bands, a first statistical estimate of the energy of a first part of an incident sound field. A gain controller processes said first statistical estimate in order to generate in frequency bands a first gain signal, and an audio processor for processing an input to the signal processing device in dependence of said generated first gain signal. The invention provides a new and improved noise reduction device and noise reduction method for use in the signal processing in devices processing acoustic signals, e.g. microphone devices.

Abstract: A transistor device having a metallic source electrode, a metallic drain electrode, a metallic gate electrode and a channel in a deposited semiconductor material, the transistor device comprising: a first layer comprising the metallic gate electrode, a first metal portion of the metallic source electrode and a first metal portion of the metallic drain electrode; a second layer comprising a second metal portion of the metallic source electrode, a second metal portion of the metallic drain electrode, the deposited semiconductor material and dielectric material between the semiconductor material and the metallic gate electrode; and a third layer comprising a substrate, wherein the first, second and third layers are arranged in order such that the second layer is positioned between the first layer and the third layer.

Abstract: Provided are a wire structure, a method for fabricating a wire, a thin film transistor (TFT) substrate and a method for fabricating a TFT substrate. The wire structure includes a barrier layer formed on a substrate and including a copper layer and a copper solid solution layer.

Abstract: It is an object of the present invention to form an organic transistor including an organic semiconductor having high crystallinity without loosing an interface between an organic semiconductor of a channel where carriers are spread out and a gate insulating layer and deteriorating a yield. A semiconductor device according to the present invention has a stacked structure of organic semiconductor layers, and at least the upper organic semiconductor layer is in a polycrystalline or a single crystalline state and the lower organic semiconductor layer is made of a material serving as a channel. Carrier mobility can be increased owing to the upper organic semiconductor layer having high crystallinity; thus, insufficient contact due to the upper organic semiconductor layer can be compensated by the lower organic semiconductor layer.

Abstract: An image processing apparatus includes a storage unit which stores volume data associated with an area including a contrast-enhanced artery as an examination target, a first calculation unit which calculates a plurality of partial atherosclerotic indexes associated with a plurality of portions of the artery on the basis of morphological information associated with the artery which is obtained from the volume data, a second calculation unit which calculates a whole atherosclerotic index associated with the entire artery including the plurality of portions on the basis of the morphological information associated with the artery, and a display unit which displays evaluation information based on the calculated whole atherosclerotic index.

Abstract: Disclosed is a semiconductor structure, which includes a non-planar varactor having a geometrically designed depletion zone with a taper, as to provide improved Cmax/Cmin with low series resistance. Because of the taper, the narrowest portion of the depletion zone can be designed to be fully depleted, while the remainder of the depletion zone is only partially depleted. The fabrication of semiconductor structure may follow that of standard FinFET process, with a few additional or different steps. These additional or different steps may include formation of a doped trapezoidal (or triangular) shaped silicon mesa, growing/depositing a gate dielectric, forming a gate electrode over a portion of the mesa, and forming a highly doped contact region in the mesa where it is not covered by the gate electrode.

Abstract: An image sensor pixel includes a semiconductor layer, a photosensitive region to accumulate photo-generated charge, a floating node, a trench, and an entrenched transfer gate. The photosensitive region and the trench are disposed within the semiconductor layer. The trench extends into the semiconductor layer between the photosensitive region and the floating node and the entrenched transfer gate is disposed within the trench to control transfer of the photo-generated charge from the photosensitive region to the floating node.

Abstract: According to an embodiment, there is provided a fabricating method for a thin film transistor substrate divided into a display area displaying images and a non-display area beside the display area, the fabricating method comprising: forming a gate wire in the display area, a common voltage line for a MPS (mass production system) test in the non-display area, and a grounding line for the MPS test in the non-display area with same material at the same time; forming a gate insulating layer covering the gate wire and a first insulating layer covering the common voltage line for the MPS test and the grounding line for the MPS test with same material at the same time; forming a data wire crossing the gate wire and defining a pixel area in the display area; and forming a pixel electrode in the pixel area and an electrode layer on the first insulating layer corresponding to the common voltage line for the MPS test and the grounding line for the MPS test with same material at the same time.

Abstract: A semiconductor device is formed with sub-resolution features and at least one additional feature having a relatively larger critical dimension using only two masks. An embodiment includes forming a plurality of first mandrels, having a first width, and at least one second mandrel, having a second width greater than the first width, overlying a target layer using a first mask, forming sidewall spacers along the length and width of the first and second mandrels, forming a filler adjacent each sidewall spacer, the filler having the first width, removing the filler adjacent sidewall spacers along the widths of the first and second mandrels using a second mask, removing the sidewall spacers, and etching the target layer between the filler and the first and second mandrels, thereby forming at least two target features with different critical dimensions.