Abstract: A power transistor having of a plurality of vertical MOSFET devices combined in parallel to achieve high-performance operation and methods of fabricating this device.

Abstract: A method of fabricating a semiconductor device includes forming a first chip separating groove such that its depth is less than the total depth of the wafer, forming a first metallization layer inside the first chip separating groove, thinning the wafer, forming a second chip separating groove in a region opposite the first chip separating groove of the rear surface of the wafer so that the wafer is separated into a plurality of semiconductor chips, forming metallization layer inside the second chip separating groove, forming a PHS layer on the entire rear surface of the wafer, and cutting the wafer at the chip separating groove, thereby producing a semiconductor device. The burr produced when the wafer is cut does not protrude from the rear surface of the wafer, assuring good adhesion between the semiconductor chip and a chip carrier, realizing a semiconductor device of a good heat dispersion characteristic and, therefore, of high reliability.

Abstract: To provide a technology capable of promoting property of a thin film transistor formed on a glass substrate, a silicon oxide film 102 is formed on a glass substrate 101 and an amorphous silicon film 103 is formed thereon. A nickel acetate solution including nickel element that is a metal element promoting crystallization of silicon is coated and a water film 401 is formed. A state in which the nickel element is held in contact with the surface of the amorphous silicon film 103 is realized by performing spin drying. Uniform crystal growth is carried out as shown by arrow marks 104 by performing a heating treatment. An electrically inactive layer is formed by having nickel element having a high concentration which is present at front end portions of crystal growth react with an underlayer of the silicon oxide film 102. In this way the crystalline silicon film restraining the influence of nickel element can be provide.

Abstract: A manufacturing system for individually processing semiconductor wafers through a plurality of processing stations. The system has a plurality of processing stations, a multilevel track system that interfaces with the processing stations, and guided transport vehicles that operate on the track system to move individual wafers in wafer carriers between the stations. The carriers have a storage memory that contains the required process sequence and the capability to remember the completed process steps.

Abstract: High-resistance polysilicon layers applied in 4T SRAM memory cells serving as loads, are manufactured by a simple method according to the invention. In the small-scale 4T SRAM memory cell process, it is not possible to fabricate traditional polysilicon loads manufactured by the prior art with a desired high degree of resistance. As a result, the miniaturization of 4T SRAM memory cells has been limited. However, in the method according to the invention, the lengths of polysilicon loads are greatly increased without increasing the sizes of corresponding memory cells, thereby efficiently increasing the resistance of the polysilicon loads. Therefore, this method according to invention can completely eliminate any limitation to the small-scale 4T SRAM memory cell process caused by the manufacture of the polysilicon loads as described above.

Abstract: After a field oxide film is formed on a P-type semiconductor substrate, ion implantation of boron is carried out with respect to a whole surface of the substrate so that a channel stopper layer is formed. Then, a MOS FET is formed in an active region of the semiconductor substrate. Subsequently, ion implantation of phosphorus is carried out, by using a gate electrode of the MOS FET and the field oxide film as a mask, so that impurity layers which have the same type of conductivity as that of the channel stopper layer and has a concentration lower than that of the channel stopper layer are formed right under the source/drain regions of the MOS FET between the source/drain regions and the channel stopper layer.

Abstract: A thin film transistor and a simplified manufacturing method thereof, which results in enhanced charge mobility. The thin film transistor includes: a substrate; a gate electrode on said substrate; a gate insulating layer on said substrate and said gate electrode; a doped semiconductor layer, on the gate insulating layer, which is split into a first and second portion; a first metal layer on the first doped semiconductor portion; a second metal layer on the second doped semiconductor portion; and a top semiconductor layer in a gap formed by the first and second metal layer: the first doped semiconductor portion, the second doped semiconductor portion, and the insulating layer.

Abstract: A green-blue to ultraviolet light emitting semiconductor laser having a top contact, a Bragg reflector, cladding layer, active layer, cladding layer, buffer, substrate, bottom contact and a passivation layer. The key aspect is a Ga*N material on a base structure comprising a SiC substrate selected from a group consisting of 2H-SiC, 4H-SiC and a-axis oriented 6H-SiC. Furthermore, the cladding layers have larger band gaps than the active layer and are complimentarily doped.

Abstract: Disclosed are a noise eliminating element having a junction of components of two kinds of electroconductive materials, characterized in that the absolute values of the thermoelectric power of the two kinds of materials is 50 .mu.VK.sup.-1 or higher and there is substantially no rectifying action at the junction. Both the Seebeck effect and the Paltier effect occur simultaneous and create a transient phenomena in one element. Because of the transient phenomena in one element and because of the transient phenomenon based on both effects, noises, particularly the standing wave noises generated at around output current near to zero are eliminated. The noise eliminating elements can be inserted in a magnetic circuit of a speaker circuit for acoustic equipment or in a diflecting coil circuit of an electron image display device.

Abstract: There is a bi-level bit line architecture. Specifically, there is a DRAM memory cell and cell array that allows for 6F**2 cell sizes and avoids the signal to noise problems. Uniquely, the digit lines are designed to lie on top of each other like a double decker overpass road. Additionally, this design allows each digit line to be routed on both conductor layers, for equal lengths of the array, to provide balanced impedance. Now noise will appear as a common mode noise on both lines, and not as differential mode noise that would degrade the sensing operation. Furthermore, digit to digit coupling is nearly eliminated because of the twist design.

Abstract: The invention relates to a high voltage integrated circuit with connecting metal conductors (30, 32) connected to ground or potential near ground and covered by a passivating layer (18). The invention is characterized by said passivating layer (18) being partially broken up above said metal conductors to prevent activation of parasitic MOS-transistor.

Abstract: An improved ESD cell provides in the worst case 2,000 volts HBM ESD protection using an NMOS transistor in a lightly-doped drain process. An NMOS transistor has its source connected to ground, and its drain connected through a polysilicon resistor to a pad of an integrated circuit. The pad is also connected by metal to an n+ pocket tap of an n-type epitaxial layer formed on a p-type substrate. The connection of pad metal to the pocket tap forms a second parasitic lateral bipolar junction transistor (BJT) having as a base the p-type well, having an emitter the source of the NMOS transistor, and having as its collector the pocket tap. The parasitic transistor turns on at the right moment and is able to shunt more current around the polysilicon resistor, thus giving a dramatic increase in ESD protection. In a worst case, the ESD cell can pass at a minimum of 2,000 volts, and the expected range of HBM ESD values is between 2,500 volts and 3,000 volts depending upon process variations.

Abstract: A normally-off semiconductor device with gate regions formed in a high-quality base is manufactured by forming a P.sup.+ layer in a lower surface of an N.sup.- substrate, selectively forming P.sup.+ gate regions in an upper surface of the N.sup.- substrate, forming intergate P.sup.+ regions in the upper surface of the N.sup.- substrate between the P.sup.+ gate regions, forming an N.sup.+ layer in an upper surface of an N.sup.- substrate, joining the N.sup.- substrate and the N.sup.- substrate to each other by heating them at about 800.degree. C. in a hydrogen atmosphere while the upper surface of the N.sup.- substrate and a lower surface of the N.sup.- substrate are being held against each other, and forming an anode electrode and a cathode electrode.

Abstract: A semiconductor integrated circuit device is provided which includes a memory cell M, in which a capacitance element C is added to the storage node portion of an inverter circuit composed of a drive MOSFET and a load TFT Qf. The device also includes and a bipolar transistor Tr provided as a peripheral element. A reference power supply line to be connected with the source region of the drive MOSFET Qd and an emitter electrode to be connected with the emitter region of the bipolar transistor Tr are formed of an uppermost thick polycrystal silicon film. Moreover, an intermediate thin polycrystal silicon film between the uppermost polycrystal silicon film and a first polycrystal silicon film (or polycide film) is covered in a memory cell forming region with the uppermost polycrystal silicon film. Still moreover, the uppermost polycrystal silicon film is partially silicified.

Abstract: A field emission device according to the present invention comprises a support substrate; a cathode mounted on a surface of said support substrate; a first diamond portion located on any surface of said substrate, said first diamond portion substantially having an electrical connection with said cathode; a second diamond portion located on the substrate surface on which said first diamond portion is also located, said second diamond portion including plurality of diamond protuberances; and an anode positioned spaced apart from said first and second diamond portions, wherein a space is formed between said anode and said second diamond portion.

Abstract: A bonded wafer structure has a device wafer 18 bonded to a handle wafer 10. A capacitor including a bottom plate as the surface 11 of handle wafer 10, a dielectric layer 12 and a top plate 15 is embedded in the bonded structure. A contact trench 22 extends from the surface 8 of device wafer 18 to the top plate 15 of the embedded capacitor.

Abstract: A DMOS device structure includes a lightly doped semiconductor layer of a first conductivity type, a plurality of lightly doped semiconductor regions of a second conductivity type extending from a top surface of the lightly doped semiconductor layer thereinto, source regions of the first conductivity type contained in the lightly doped semiconductor regions and defining channel regions. The lightly doped semiconductor regions are contained in respective enhancement regions of the lightly doped semiconductor layer of the same conductivity type as, but with a lower resistivity than, the lightly doped semiconductor layer.

Abstract: A semiconductor device comprising a silicon substrate, an oxide layer on the silicon substrate, a doped polysilicon region disposed on the oxide layer, a dielectric layer which has been deposited over the doped polysilicon region and the silicon substrate, a contact hole which is formed in the dielectric layer and extends over respective laterally adjacent portions of the doped polysilicon region and the silicon substrate and a contact which has been selectively deposited in the contact hole which electrically connects the said portions together.

Abstract: An infrared optical field effect transistor has been developed using a thin film of Lead Titanate (PbTiO.sub.3) deposited on a n/p.sup.+ Si substrate by RF magnetron sputtering. This transistor possesses excellent pyroelectric properties and can, therefore, be operated even at room temperature. The infrared optical field effect transistor has the following features associated with rapid bulk channel structure and higher mobility:1. Can be operated at room temperature, unlike quantum type IR sensors which can only operate at very low temperature (-100.degree. C..about.-200.degree. C.), which results in higher costs.2. High speed response with only 2.3 .mu.s of rise time. This is much faster than other types of thermal infrared optical field effect transistors.3. Easy to fabricate an integrated sensor device.

Abstract: In the vicinity of the (100) plane, planar channeling by (100) type crystal planes, which are (011) plane and (011) plane according to the (100) surface plane, degrades uniformity of ion implantation. Therefore, a major surface of the substrate is established at a plane perpendicular to a crystal orientation forming an angle greater than or equal to 3.5.degree. with two planes perpendicularly intersecting the (100) plane. Namely, in consideration of fluctuation in setting to an ion implantation device and ion implantation angle, the substrate having surface orientation within a range 104 is employed. Also, by limiting the orientation to be less than or equal to 10.degree. from the (100) plane, ion implantation can be performed perpendicularly to the substrate without modifying the process condition.