Abstract: A technique for manufacturing a semiconductor device includes the steps of preparing a stepped substrate made of a group III-V compound semiconductor and having a flat surface exposing a (1 0 0) plane and a slanted surface exposing an (n 1 1)B plane whrerein n is a real number of about 1.ltoreq.n, and epitaxially growing the group III-V compound semiconductor to form an epitaxial layer on the surface of the stepped substrate while doping p- and n-type impurities, selectively at the same time or, alternatively, under conditions such that the grown epitaxial layer has an n-type region on the slanted surface and a p-type region on the flat surface.

Abstract: A nonvolatile semiconductor memory device includes an array of a plurality of memory cells formed in a semiconductor substrate and arranged in a matrix of columns and rows, word lines each being formed to include control gates of the memory cells arranged in each row, a plurality of bit lines, each being connected to drains of the memory cells arranged in one column, and a plurality of source lines, each being connected to sources of the memory cells arranged in one column; wherein adjacent two memory cells arranged in each row have the source or drain in common; and each of the plurality of bit lines is connected selectively to one of adjacent two main bit or source lines through a switching circuit.

Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel s

Abstract: A semiconductor device is provided for convenient checking of etching states of semiconductor layers, along with a process for its preparation, wherein a test layer is formed on the same wafer where a semiconductor product is manufactured, and concurrently with and under the same formation conditions as formation a target layer forming a part of the semiconductor product, wherein the test layer is formed on a first layer and on a second layer interposed between a portion of the test layer and the first layer, with one of the first and second layers having the same etching properties as the target layer and the other of the first and second layers having different etching characteristics from the target layer.

Abstract: Elevated source and drain regions epitaxially grown on both sides of a gate structure cause a dopant impurity to form an extremely shallow p-n junctions in a semiconductor substrate so as to prevent a field effect transistor from a short channel effect, and side wall spacers include pad layers of silicon nitride and spacer layers of silicon oxide formed on the pad layers so that the elevated source and drain regions form boundaries to the pad layers without a facet and a silicon layer on the spacer layers.

Abstract: A MISFET having a graded semiconductor alloy channel layer of silicon germanium in which the germanium is graded to a single peak percentage level. The single peak percentage level defines the location of the charge carriers within the layer. The transconductance of the device can be optimized by controlling the location of the carriers within the channel.

Abstract: A semiconductor memory cell device exhibiting superior cell reliability comprising a dual layer floating gate wherein the thin upper layer of the floating gate overlaps the edges of surrounding field insulating regions and has rounded edges to minimize leakage concerns. The tunnel dielectric separating the dual layer floating gate from the substrate comprises a layer of uniform thickness which is grown prior to the formation of the field insulating regions. The Fowler-Nordheim tunneling mechanism is used for programming and erasing the inventive cells in a programming process flow which comprises flash programming all cells on a word line, sensing current on a selected cell, and selectively erasing the charge on the cell by applying a higher voltage on the intersecting bit line than is applied to the word line, until the sensed current is as desired.

Abstract: A self-aligned polysilicon thin film transistor, and a method for manufacturing it, is described. An insulating substrate is provided. A gate electrode is formed on the insulating substrate. A protective light-absorbing layer is formed over the gate electrode and over the insulating substrate. The protective light-absorbing layer is patterned. A gate dielectric layer is formed over the protective light-absorbing layer and over the insulating substrate. A layer of amorphous silicon is formed over the gate dielectric layer. A photoresist mask is formed over the layer of amorphous silicon, aligned with the protective light-absorbing layer. The amorphous silicon layer is implanted with a conductivity-imparting dopant in source/drain regions not protected by the photoresist mask. The photoresist mask is removed. The amorphous silicon layer is laser-annealed, whereby doped polysilicon is formed in the source/drain regions, and undoped polysilicon is formed in areas between the source/drain regions.

Abstract: In a device (101) formed as an invertor, terminals connected to floating source pins (VS) which are provided in control circuits (31 to 33) are limited to output terminals (U, V, W). In order to hold voltages across floating source pins (VD, VS), capacitive elements (51 to 53) which are provided around the device (101) are connected to the output terminals (U, V, W). Thus, the terminals which are connected with the floating source pins (VS) are shared by the output terminals (U, V, W), whereby the numbers of the terminals and wiring patterns are reduced. Thus, the device (101) is miniaturized.

Abstract: A power IC having at least a level shifter for changing the level of an input signal, a high-side driver circuit for driving a predetermined load in accordance with a level changed by the level shifter, the high-side driver circuit being in a floating state, and a reverse current preventing diode for disconnecting a current path from the ground of the level shifter to the reference potential of the high-side driver circuit. The high-side driver circuit and reverse current preventing diode are respectively dielectrically isolated by a dielectric member to prevent insufficient element isolation to be caused by bias conditions. The predetermined reference potential to be connected to an inductive load or the like in the high-side driver circuit can be set to a negative potential. The electrical energy stored in the inductive load or the like can be extracted out and attenuated at high speed via the reference potential set to the negative potential to thereby realize a high speed operation.

Abstract: A nonvolatile storage element of single-layer gate structure constructed by arranging a floating gate formed of a conductive layer to partly overlap with a control gate formed of a diffused layer is provided with a barrier layer covering a part or the whole of the surface of the floating gate. Such nonvolatile storage elements are used for redundancy control of defects or change of functions.

Abstract: The present invention provides a silicon on insulator type semiconductor device including a transistor, a diode and a power source line. The transistor includes an insulator, a silicon film with which the insulator is selectively covered to form a device formation region, a gate insulating film with which the device formation region is covered, a gate electrode formed on the gate insulating film, a region having first conductivity and formed in the silicon film below the gate electrode across the gate insulating film, and source and drain regions both having second conductivity and formed in the silicon film in self-aligned fashion about the gate electrode so that the region is sandwiched between the source and drain regions. The diode is in electrical connection with the transistor through the drain region. Both the diode and the source region of the transistor are electrically connected to the power source line.

Abstract: A semiconductor device includes an Si substrate, a stress absorbing layer of GaAs and disposed on the Si substrate, a buffer layer having a composition of Al.sub.x Ga.sub.1-x-y In.sub.y N (0.ltoreq.x.ltoreq.1, 0.ltoreq.y.ltoreq.1) and disposed on the stress absorbing layer, and a compound semiconductor layer having a composition of Al.sub.x Ga.sub.1-x-y In.sub.y N (0.ltoreq.x.ltoreq.1, 0.ltoreq.y.ltoreq.1) and disposed on the buffer layer. Therefore, the buffer layer protects the GaAs stress absorbing layer from high temperatures during the formation of the compound semiconductor layer, whereby the stress absorbing layer is prevented from decomposition. As a result, a stress due to lattice mismatch or thermal stress between the Si substrate and the compound semiconductor layer is absorbed in the GaAs stress absorbing layer having a lowest bulk modulus, whereby a compound semiconductor layer with reduced dislocations may be grown on the buffer layer and bending of the Si substrate prevented.

Abstract: A device and a method of manufacture of a semiconductor device on a semiconductor substrate including an SRAM cell with a resistor comprises forming a first polycrystalline silicon containing layer on the semiconductor substrate, patterning and etching the first polycrystalline silicon containing layer to form steps on either side thereof, forming a dielectric layer over the first polycrystalline silicon containing layer with the steps on either side of the first polycrystalline silicon containing layer, forming a blanket of a second polycrystalline silicon containing layer extending over the interpolysilicon layer, and ion implanting the second polycrystalline silicon containing layer in a blanket implant of a light dose of dopant including ion implanting resistive regions with far higher resistivity in the regions over the steps.

Abstract: Semiconductor radial rays detector is provided that improves a breakdown voltage yield of a gate insulating film of a semiconductor radial rays detector and prevents an increase in resistance of a gate electrode caused by the improvement in the breakdown voltage yield. In the inventive semiconductor radial rays detector, material used as a gate electrode 1 of a reading condenser is not an Al film (aluminum film) but a POLY Si film (a polycrystalline silicon film), or silicide or metal including silicide with a high melting point such as WSi (tungsten silicide) (strictly its composition is indefinite as expressed as W.sub.x Si.sub.y) or TiSi (titan silicide) (expressed as Ti.sub.x Si, in the same manner).

Abstract: A thin film transistor which can improve such electric characteristics as off current characteristics, and a manufacturing method of a thin film transistor. A thin film transistor (110) has an n.sup.- source area (112) and an n.sup.- drain area (113) consisting of an n.sup.- silicon film (low concentration area) of about 400 .ANG., which is a silicon film made by performing a crystallization treatment such as an SPC method on an amorphous silicon, and the crystallization treatment is carried out after the implantation of impurities to activate the impurities at the same time. A gate electrode (116) is a metal electrode, and is formed after an n.sup.- source area (112) and an n.sup.- drain area (113) are formed. A gate electrode (116), an n.sup.- source area (112) and an n.sup.- drain area (113) are not formed self-alignedly.

Abstract: An image-forming member for electro-photography has a photoconductive layer comprising a hydrogenated amorphous semiconductor composed of silicon and/or germanium as a matrix and at least one chemical modifier such as carbon, nitrogen and oxygen contained in the matrix.

Abstract: A semiconductor processing method of forming complementary metal oxide semiconductor memory circuitry includes, a) defining a memory array area and a peripheral area on a bulk semiconductor substrate, the peripheral area including a p-well area for formation of NMOS peripheral circuitry, the peripheral area including a first n-well area and a second n-well area for formation of respective PMOS peripheral circuitry, the first and second n-well areas being separate from one another and having respective peripheries; b) providing a patterned masking layer over the substrate relative to the peripheral first and second n-wells, the masking layer including a first masking block overlying the first n-well and a second masking block overlying the second n-well, the first masking block masking a lateral edge of the first n-well periphery; and c) with the first and second masking blocks in place, providing a buried n-type electron collector layer by ion implanting into the bulk substrate; the resultant n-type electron

Abstract: A device and a method are provided for manufacture of that semiconductor memory device on a silicon semiconductor substrate with a vertical channel. A dielectric layer pattern with openings through it is formed. Trenches are formed in the surface of the semiconductor substrate. The trenches have sidewalls. A spacer layer is formed on the surface of the device. The spacer layer is shaped to form spacers in the trenches on the sidewalls. Source/drain regions are formed by ion implanting ions to deposit dopant into the substrate. The device is annealed to form source/drain regions in the substrate. A dielectric layer is formed over the device. A conductive word-line is formed and patterned over the dielectric layer.

Abstract: The semiconductor device according to the present invention includes a semiconductor substrate of a first conductive type. A well area of the first conductive type is formed in the substrate. The well area has higher concentration of impurity than that of the substrate. The well area includes a first element. The first element is of a second conductive type different from the first conductive type. A second element of the second conductive type formed in the substrate. The first element is isolated from the second element by a field oxide.