Abstract: An image sensor includes a substrate on which a light-receiving element and a thin-film transistor for transferring an output from the light-receiving element are formed, and a silicon integrated circuit chip for driving the thin-film transistor and processing signals. All externally connected input/output signal lines are extracted through or electrical connections to the silicon integrated circuit chip.

Abstract: A process for stripping the outer edge of a bonded BESOI wafer. The bonded BESOI wafer comprises a handle wafer, an oxide layer on one surface of the handle wafer, a device layer bonded to the oxide layer, and a p.sup.+ etch-stop layer on the device layer having an exposed face. The process comprises masking the exposed face of the p.sup.+ etch-stop layer, and abrading the periphery of the BESOI wafer to remove edge margins of the p.sup.+ etch-stop layer and device layer.

Abstract: An asymmetrical vertical lightly doped drain metal oxide semiconductor field effect transistor (VLDD MOSFET) is formed on a semiconductor substrate. The substrate includes first and second main planar surfaces with the second main planar surface parallel to and positioned at a height lower that the first main planar surface. A third planar surface, generally normal to the first and second main planar surfaces, connects the first and second main planar surfaces on the drain region side of the channel region. The source region is formed in a portion of the first main planar surface, and the drain region is formed in the third planar surfaces and portions of the first and second main planar surfaces. Contours of equal ion concentration in the drain region are non-Gaussian and an interface between the channel region and drain region is generally linear beneath the gate electrode adjacent the generally normal third planar surface.

Abstract: A semiconductor device having: a semiconductor substrate of a first conductivity type; a well formed in a surface of said semiconductor substrate, the welt being of a second conductivity type opposite to the first conductivity type; a first MOS transistor formed in a surface of a first conductivity type region of the semiconductor substrate; a second MOS transistor formed in a surface of the well; a wiring connected to the gate electrodes of the first and second MOS transistors; and a protection diode with a p-n junction formed in the first conductivity type region and comprising a second conductivity type region electrically connected to the wiring and the first conductivity region of the semiconductor substrate, wherein the wiring and the well are not directly connected electrically. A CMOS type semiconductor integrated circuit device with a long and wide area wiring is realized which can effectively suppress damage to a gate oxide film of a MOSFET.

Abstract: An insulated gate semiconductor device has a semiconductor substrate having an irregular surface of raised portions and depressed portions, and a main device region and a protective circuit region. The protective circuit region is formed in a raised portion of the semiconductor substrate and includes a semiconductor device which is driven by an insulated gate electrode formed in a depressed portion of the semiconductor substrate. The raised portions and the depressed portions of the semiconductor substrate are formed by a trench etching method.

Abstract: A semiconductor IC comprising a supporting substrate; a first buried insulator film formed partially on the supporting substrate; a second buried insulator film thinner than the first buried insulator film formed partially on the supporting substrate; a plurality of island-shaped semiconductor layers formed on the first and second buried insulator films, respectively; and dielectric isolation regions formed between the plurality of island-shaped semiconductor layers. A surge protection circuit is formed in the island-shaped semiconductor layer formed on the second buried insulator film and also an internal circuit is formed in other island-shaped semiconductor layers formed on the first buried insulator film. Surface wirings are disposed to interconnect the surge protection circuit and the internal circuit.

Abstract: An optical semiconductor device comprises a stripe-mesa structure provided on a semi-insulating substrate. The stripe-mesa structure comprises an undoped light absorption layer sandwiched by cladding layers, and by burying layers on both sides. With this structure, the device capacitance is decreased to provide wide bandwidth and ultra-high speed operation properties. This device can be applied to an optical modulator, an integrated type optical modulator, and an optical detector.

Abstract: An interposer (preformed planar structure) is disposed between a die and a substrate (which may be another die). Through holes in the interposer facilitate controlled formation of electrical connections between the die and the substrate. In one embodiment, the through-holes in the interposer are filled flush with a resilient plastic conductive material and pressed against raised conductive structures on the die and substrate. The die, interposer, and substrate are maintained in electrical contact under compression. The compressing force can be removed to replace the die. In another embodiment, the interposer has embedded conductive elements which make contact with selected connections between the die and the substrate. Electrical connections between the conductive elements can be selectively effected to provide for "re-wiring" of connections to the die and substrate.

Abstract: A symmetrical vertical lightly doped drain metal oxide semiconductor field effect transistor (VLDD MOSFET) is formed on a semiconductor substrate. The substrate includes a first region having a generally planar upper surface and a second region, projecting upwardly from the first region and having a generally planar upper surface, the second substrate region having opposed sidewalls generally normal to the upper surface of the first substrate region. A gate electrode is formed through an insulating film on the upper surface of the second substrate region, source/drain impurity regions are formed in the substrate on opposite sides of said gate electrode, and a channel region is formed under the gate electrode between the source/drain regions. Contours of equal ion concentration in the source/drain regions are non-Gaussian and an interface between the channel region and each source/drain region is generally linear beneath the gate electrode adjacent the opposing sidewalls of the second substrate region.

Abstract: In a flash type EEPROM device, when a dose amount of an impurity of a floating gate is controlled, or, a channel of a transistor is buried by an ion implantation, the threshold value at no charges accumulated is set between the threshold at writing and the threshold at erasure, to reduce the disturbances of a drain and a gate when reading.

Abstract: A field shield element for isolating semiconductor devices formed on a common substrate. The field shield element comprises an electrode of a high melting point metal which may have a reduced thickness and which avoids punch through of a connection point through the field shield electrode during manufacture. By employing the shield gate electrode metal having a high melting point, the reduction in thickness of the shield gate electrode provides a corresponding reduction in thickness of the offset existing between the semiconductor device and the isolation structure formed with the field shield element. The shield gate electrode may be combined with metal silicon compounds, and metal nitrides to realize the foregoing benefits of avoiding punchthrough and reducing the offset.

Abstract: A heterojunction is formed between a pair of layers of different semiconductive materials whose work function difference produces a large band offset at the heterojunction. Donor or acceptor atoms are included in one regions that when photoexcited produce free charge carriers but leave behind charged centers that keep the photoexcited carriers localized. The large barrier at the heterojunction limits recombination of the free charge carriers and the charged centers and persistent photoconductivity results. This effect is used to form light operated switches. An illustrative example uses a layer of high purity gallium arsenide forming a heterojunction with a gallium-doped layer of zinc selenide.

Abstract: A non-volatile memory device is fabricated having enhanced charge retention capability. Enhanced charge retention is achieved upon the floating gate of the non-volatile memory device. The floating gate can be configured as a stacked or non-stacked pair of polysilicon conductors. In either instance, negative charge programmed upon the floating gate is retained by reducing the presence of positively charged atoms within dielectrics overlying the floating gate conductor. Moreover, diffusion avenues of the positively charged hydrogen are reduced by maintaining a prevalence of relatively strong bond locations within the overlying dielectric layers. Thus, origination of positively charged atoms such as hydrogen from those bonds is substantially prevented by processing the hydrogen-containing dielectrics at relatively low temperatures and further processing any subsequent dielectrics and/or conductors overlying the floating gate at relatively low temperatures.

Abstract: An integrated circuit chip is provided having an electrical circuit formed therein. A plurality of devices is formed in an active device region of the chip, such devices being connected as active devices. A plurality of additional ones such device are formed in a region adjacent to the active device region, such additional ones of the devices being connected as passive devices. The additional devices provide a dual purpose: first there presence improves the electrical characteristic matching among the devices which are to provide the active devices for the circuit; and, second, they are available to provide passive devices for use by the circuit rather then merely taking up space as a mere "dummy" previously unused by the circuit. More particularly, a plurality of first devices is formed in an active device region of the chip to provide the active devices. Each one of such first devices has the same shape and size.

Abstract: A semiconductor memory which includes first and second memory cells, wherein the first memory cells include first MOS transistors each having impurity diffused layers provided inside of both of a source and a drain to expanding source and drain regions, the second memory cells include second or third MOS transistors each having an impurity diffused layer provided inside of one of a source and a drain or include fourth MOS transistors each having no impurity diffused layer provided inside of either thereof, as well as a method for fabricating the semiconductor memory. Differences in threshold voltage between the first and second to fourth MOS transistors are utilized as differences in storage status between the first and second memory cells so that data "0" or "1" is stored in each memory cell.

Abstract: An arrangement of non-volatile memory cells, such as flash memory cells which includes erase blocks which can be separately erased and which require a reduced amount of circuit area. The erase blocks each include an array of the cells arranged in rows and columns. Each cell in a row has its control gate connected to a common word line and its drain connected to a common bit line. All of the sources of one of the erase blocks are connected together by a source line structure which includes non-metallic source lines, such as doped semiconductor lines, which run generally parallel with respect to the word line and interconnect the sources of cell located in a row. The source line structure further includes at least one metallic source line which functions to interconnect the source regions of cells located in one of the erase block cell columns.

Abstract: A method for forming an ESD protection device, with reduced junction breakdown voltages, while simultaneously forming an integrated circuit, containing FET devices, has been developed. This invention features forming a large area, ESD protection diode, by using a first ion implantation step, of a specific conductivity type, also used for the heavily doped source and drain regions of attached FET devices. After photoresist processing, used to mask the attached FET devices, a second ion implantation step, opposite in conductivity type then the first implant, is used to complete the ESD protection diode, for the ESD protection device. This large area diode reduces junction breakdown voltage, while allowing ESD current to be discharged more efficiently then for smaller ESD protection counterparts.

Abstract: A high density non-volatile ferroelectric-based memory based on a ferroelectric FET operated in a two terminal write mode. Storage words may be constructed either from one or two bit storage cells based on a ferroelectric FET. A memory using either the one or two bit storage cells includes a plurality of word storage cells organized into a rectangular array including a plurality of columns and rows. Each of the word storage cells includes N single bit memory cells. Each of the single bit memory cells includes a pass transistor and a ferroelectric storage element. All of the gate electrodes in the circuit are connected to a common gate electrode, and all of the source electrodes are connected to a common source electrode. If the memory is built from two bit storage cells as described herein, each storage cell is one half of a two bit storage cell.

Abstract: A moisture impervious film 24 such as silicon nitride is formed under an interlayer insulating film, covering the active region of an IC chip. The interlayer insulating film is formed, for example, by lamination of a silicon oxide film, a spin-on-glass (SOG) film, and another silicon oxide film. Moisture (H.sub.2 O) is intercepted by the moisture impervious film and does not reach the active region. It is possible to avoid the conductivity type inversion at the surface of a p-type well region in the active region and to suppress the corrosion of wiring layers, improving the reliability of the IC chip. The moisture impervious film is not limited to be formed at the layer under the silicon oxide film, but it is sufficient only if the film is formed at the layer under the SOG film.

Abstract: Each of source regions (4) is provided only immediately below a bottom surface (3B) of each of trenches (3) which is formed in a silicon substrate (1), extending inward from a main surface (1S) thereof along a second direction, and each of gate electrode portions (23) is provided inside each of the trenches (3). Specifically, each of the gate electrode portions (23) consists of a gate oxide film (19) formed on a side surface (S1) and part of the bottom surface (3B) of the trench (3), an FG electrode (20) formed thereon, a gate insulating film (21) formed on a side surface of the FG electrode (20) which is out of contact with the gate oxide film (19), an upper surface of the FG electrode (20), a side surface (2S) and the other part of the bottom (3B) of the trench (3), and a CG electrode (22) formed so as to cover an upper surface of the gate insulating film (21). Each of drain regions (11) is shared by the two adjacent transistors.