Abstract: A semiconductor device having an integrated circuit with high density load elements in memory cells forming a memory array wherein the load elements are either of the active (e.g., TFTs) or passive (e.g., resistance) type and designed so that the connection path between these elements and active element domains is extended to be longer within the same or smaller scale of the memory cell configuration. For this purpose, the connection path may be made to meander to provide for greater length, i.e., extend in one direction and then another within a single memory cell configuration. This further creates additional space for extending the resistance value of the active or passive load element which, in turn, permits a reduction in drain current, i.e., current consumption, during operational conditions of the memory cells or other circuits.

Abstract: In integrated structure sensing resistor for a power MOS device consists of a doped region extending from a deep body region of at least one cell of a first plurality of cells, constituting a main power device, to a deep body region of a corresponding cell of a second smaller plurality of cells constituting a current sensing device. The first plurality of cells and the second plurality of cells are formed using trench technology.

Abstract: An SOI transistor whose source region and/or drain region have a heterostructure made up of at least two different semiconductor materials, to thereby prevent a bipolar-induced breakdown.

Abstract: A DMOS device structure, and method of manufacturing the same features a self-aligned source and body contact structure which requires no additional masks. Polysilicon spacers are used to form the source region at the periphery of the gate polysilicon. The preferred method of manufacturing uses five masks to produce a discrete DMOS semiconductor chip. An N- epitaxial layer is grown on an N+ substrate. Thick field oxide is grown. A first mask is used to etch an active region. Thin gate oxide is grown. Doped polysilicon is then deposited. A second mask is used to etch the polysilicon, thereby forming the gates. Insulating oxide is grown. A blanket P body implantation is performed. A thermal drive-in step laterally and vertically diffuses the implanted P type impurity throughout body regions. The insulating oxide is etched. A polysilicon layer is deposited and doped. A dry etch leaves polyslicon spacers along the edges of the gates.

Abstract: A thick oxide layer is formed over a drain region of an MOS transistor while a thin oxide layer is provided over the source and channel regions. As a result both improved current driving ability and reduced gate induced drain leakage current are achieved.

Abstract: A heterojunction bipolar transistor has a support substrate, a collector layer formed on the support substrate, a base layer formed on the collector layer containing arsenic as group V element, a first emitter layer formed on the base layer, containing phosphorus as group V element, and having a band gap wider than the base layer, an emitter passivation layer formed on the first emitter layer made of semiconductor having a function of passivating the surface of the first emitter layer, and a base electrode forming an ohmic contact with the base layer. The whole upper surface of the base layer is covered with the first emitter layer and base electrode, the whole upper surface of the first emitter layer is covered with the emitter passivation layer, and the region of the first emitter layer adjacent to the edge of the base electrode is depleted throughout the full depth thereof.

Abstract: In a semiconductor integrated circuit having a plurality of electronic circuits each provided with interfaces used for effecting signal transmission, and supplied with operating voltages from a plurality of independent power supply terminals, protective elements each having high threshold voltages at which the elements are off in the ordinary state of power supply are provided, and a resistor and a diode both for preventing electrostatic breakdown are connected to the gate of an input MOSFET of the interface for carrying out signal transmission between the electronic circuits. Even when a high voltage due to static electricity is applied to each power supply terminal while the semiconductor integrated circuit is handled, electrostatic breakdown of the interface can be prevented by the protective element or the electrostatic breakdown preventive circuit comprising a resistor and a diode.

Abstract: A high performance transistor includes mesa structures in a conduction region, favoring corner conduction, together with lightly doped mesa structures and mid-gap gate material also favoring operation in a fully depleted mode. Mesa structures are formed at sub-lithographic size and pitch as recesses or by epitaxial growth together with exposure of a resist by an interference pattern generation with illuminating radiation and multiple exposures using a mask shifted by a sub-lithographic distance. For an NFET, conduction electron and hole distribution profiles in the mesa structures and gate capacitance are adjusted with dielectric thickness, including deposition of oxide from a liquid solution at room temperature. Transconductance may be altered by change of the aspect ratio of the mesa structures. Lightly doped drain structures are also formed at sub-lithographic sizes by self-aligned processes.

Abstract: A semiconductor body (2) has an active region (6) of n conductivity type formed of a material having a relatively low mass, high mobility conduction band main minimum and at least one relatively high mass, low mobility conduction band satellite minimum and an injector region (9) defining a potential barrier (P) to the flow of electrons into the active region (6) of a height such that, in operation of the device, electrons with sufficient energy to surmount the barrier (P) provided by the injector region (9) are emitted into the active region (6) with an energy comparable to that of the at least one relatively high mass, low mobility conduction band satellite minimum. An electron containing well region (10a, 10b) of a material different from that of the active region (6) and of the injector region (9) is provided between the injector region (9) and the active region (6) for inhibiting the spread of a depletion region into the active region (6) during operation of the device.

Abstract: An image sensor includes a substrate on which are formed a light-receiving element and a thin-film transistor for transferring an output from the light-receiving element, and a silicon integrated circuit chip for driving the thin-film transistor and processing signals. All externally connected input/output signal lines are extracted through or electrically connected to the silicon integrated circuit chip.

Abstract: An FET having a high breakdown voltage comprises a P type semiconductor substrate (5), a plurality of pairs of source regions (S) and drain regions (D) each comprising N.sup.- impurity layers (3) formed in the substrate, gate electrodes (9) each formed through an insulating film over a region interposed between each of the source regions and each of the drain regions, N.sup.+ impurity diffused layers (4) formed, shifted by a constant dimension in the N.sup.- impurity diffused layers, a source terminal (7a) connecting a plurality of source regions and a drain terminal (7b) connecting a plurality of drain regions in the plurality of pairs such that a dimensional error caused by shifting is compensated for.

Abstract: A method for forming an ohmic interface between unipolar (isotype) compound semiconductor wafers without a metallic interlayer and the semiconductor devices formed with these ohmic interfaces are disclosed. The ohmic interface is formed by simultaneously matching the crystallographic orientation of the wafer surfaces and the rotational alignment within the surfaces of the two wafers and then subjecting them to applied uniaxial pressure under high temperatures to form the bonded ohmic interface. Such an ohmic interface is required for the practical implementation of devices wherein electrical current is passed from one bonded wafer to another.

Abstract: A quantum wire structure includes a first layer having a thickness sufficiently smaller than a de Broglie wavelength of an electron wave in a medium, a second layer and a third layer which are disposed on and under the first layer and respectively have a forbidden band width larger than that of the first layer, wherein the first layer has a region with a relatively small curvature and a region with a relatively large curvature in its cross-section, and a width of the region with a relatively small curvature is 50 nm or less.

Abstract: A field effect semiconductor device comprises a first channel layer composed of an undoped semiconductor in which electrons mainly drift in low-noise operation and a second channel layer composed of a semiconductor of one conductivity type in which electrons mainly drift in high-power operation, a third channel layer being provided in the second channel layer or on the second channel layer on the opposite side of the first channel layer. The third channel layer is constituted by at least one semiconductor layer of the one conductivity type or undoped having a greater electron affinity than that of the second channel layer and having a smaller forbidden bandgap than that of the second channel layer. In another field effect semiconductor device, an undoped impurity diffusion preventing layer having an electron affinity approximately equal to that of the second channel layer is provided between the first channel layer and the second channel layer.

Abstract: A dynamic random access memory device includes a storage capacitor having a plurality of stacked conductive films which form a storage electrode. A gap is formed between elevationally adjacent conductive films so as to surround the storage electrode. A gap is also formed between an insulating film which covers a gate electrode for insulation and a lowermost film of the storage electrode. Connection between the adjacent films may be established so that an uppermost film elevationally extends so as to make contact with a drain region. Also, connection can be established so that an upper film is mounted directly on an lower film. An end portion of the film may be thicker than the other portion thereof. The stacked film structure may be produced by alternatively forming a film made of a material different from the insulating film covering the gate electrode, and a conductive film.

Abstract: Hermetically sealed chip packages are described which are capable of withstanding elevated temperatures and accompanying temperature fluctuations. The chip packages feature electrically conductive, hermetic vias which provide electrical pathways through generally dielectric ceramic substrates employed in the chip package. Methods of forming such hermetic vias are also disclosed.

Abstract: A controllable infrared filter (22) includes a quantum well filter unit (24) operable to absorb infrared energy at a selected wavelength. The quantum well filter unit (24) has a quantum well layer (26) made of an infrared transparent semiconductor mate rial and a barrier layer (28, 32) of another infrared transparent semiconductor material epitaxially deposited on each side of the quantum well layer (26). There is structure for controllably introducing charge carriers into the quantum well layer (26), which may utilize a source of electrons from other semi conductor layers (36, 38) and an applied voltage, or may utilize a laser (76) that generates charge carriers in the quantum well layer (26). The filter (22) further includes a lens (44, 46) or other optical system for directing infrared radiation through the first barrier layer (28), the quantum well layer (24), and the second barrier layer (32). Fixed band pass optical filters may be used in conjunction with the controllable quantum well filters.