Abstract: A display device includes a sensing line and a data driver. The sensing line is in a display panel. The data driver includes a plurality of integrated circuits. Each of the integrated circuits includes an interface, which includes a mobile industry processor interface (MIPI) and a crack detector. The crack detector detects cracks of the panel based on the sensing line and transmits and receives information corresponding to the crack to and from adjacent ones of the integrated circuits using a transmission terminal and a reception terminal in the MIPI.

Abstract: A semiconductor memory device according to an embodiment includes a substrate, conductive layers, pillars, and contacts. The substrate includes first and second areas, and block areas. The conductive layers are divided for each of the block areas. The conductive layers includes terraced portions. The contacts are respectively provided on the terraced portions for each of the block areas. The second area includes a first sub area and a second sub area. The first sub area includes a first stepped structure. The second sub area includes a second stepped structure and a first pattern. The first pattern is continuous with any one of the conductive layers. The first pattern is arranged between the first stepped structure and the second stepped structure.

Abstract: Laterally-gated transistors and lateral Schottky diodes are disclosed. The FET includes a substrate, source and drain electrodes, channel, a gate electrode structure, and a dielectric layer. The gate electrode structure includes an electrode in contact with the channel and a lateral field plate adjacent to the electrode. The dielectric layer is disposed between the lateral field plate and the channel. The lateral field plate contacts the dielectric layer and to modulate an electric field proximal to the gate electrode proximal to the drain or source electrodes. Also disclosed is a gate electrode structure with lateral field plates symmetrically disposed relative to the gate electrode. Also disclosed in a substrate with dielectric structures buried in the substrate remote from the gate electrode structure. A lateral Schottky diode having an anode structure includes an anode (A), cathodes (C) and lateral field plates located between the anode and the cathodes.

Abstract: A micro multi-color LED device includes two or more LED structures for emitting a range of colors. The two or more LED structures are vertically stacked to combine light from the two more LED structures. Light from the micro multi-color LED device is emitted horizontally from each of the LED structures and reflected upward via some reflective structures. In some embodiments, each LED structure is connected to a pixel driver and/or a common electrode. The LED structures are bonded together through bonding layers. In some embodiments, planarization layers enclose each of the LED structures or the micro multi-color LED device. In some embodiments, one or more of reflective layers, refractive layers, micro-lenses, spacers, and reflective cup structures are implemented in the device to improve the LED emission efficiency. A display panel comprising an array of the micro tri-color LED devices has a high resolution and a high illumination brightness.

Abstract: Systems and methods for building passive and active electronics with diamond-like carbon (DLC) coatings are provided herein. DLC may be layered upon substrates to form various components of electronic devices. Passive components such as resistors, capacitors, and inductors may be built using DLC as a dielectric or as an insulating layer. Active components such as diodes and transistors may be built with the DLC acting substantially like a semiconductor. The amount of sp2 and sp3 bonded carbon atoms may be varied to modify the properties of the DLC for various electronic components.

Abstract: A semiconductor device has a semiconductor substrate and a semiconductor film doped with impurities that is formed so as to cover an inner wall surface of a trench formed so as to extend from a first surface of the semiconductor substrate towards an interior thereof. The semiconductor film is formed so as to extend continuously from the inner wall surface to the first surface of the semiconductor substrate. The semiconductor device further has an opposite electrode having a first portion that is provided at a position opposing the semiconductor substrate while sandwiching the semiconductor film therebetween, and that extends on the first surface of the semiconductor substrate, and a second portion that is continuous with the first portion and extends so as to fill the trench. The semiconductor device further has an insulating film that insulates the semiconductor film from the opposite electrode.

Abstract: An OLED panel includes a display area and a non-display area around the display area; a substrate, a driving device layer and a light emitting device layer arranged in the display area, an encapsulation layer covering the light emitting device layer; and a touch layer located on a side of the encapsulation layer facing away from the substrate, the touch layer comprising a touch electrode and a touch wire. The non-display area includes an electrostatic discharge portion, the electrostatic discharge portion is made of a conductive material and is located on a side of the encapsulation layer facing away from the substrate. The non-display area includes a blocking portion, the blocking portion is arranged around the display area, and is located between the substrate and the encapsulation layer. The electrostatic discharge portion is located on a side of the touch wire facing away from the display area.

Abstract: A semiconductor memory device includes a first stacked structure, a first supporter layer, a second stacked structure, a block cut structure, and a second supporter layer on the second stacked structure and separated by a second cut pattern. The first stacked structure includes a first and second stack, the second stacked structure includes a third stack separated by the block cut structure and a fourth stack, the first supporter layer is on the first stack and the second stack, the second supporter layer is on the third stack and the fourth stack, the first cut pattern includes a first connection on the block cut structure and connecting the first supporter layer and the second stack, and the second cut pattern of the second supporter layer includes a second connection on the block cut structure and connecting the second supporter layer placed on the third stack and the fourth stack.

Abstract: A perovskite light-emitting diode and a method of manufacturing the same are provided. The method includes steps of providing a substrate, disposing a first electrode layer, a hole transport layer, and a perovskite precursor liquid layer on the substrate, coating the perovskite precursor liquid layer with a first solvent, performing a first thermal process to form a perovskite prefabricated layer, coating the perovskite prefabricated layer with a second solvent, and performing a second thermal process to form a perovskite light-emitting layer.

Abstract: A device includes a first channel layer, a second channel layer, a gate structure, a source/drain epitaxial structure, and a source/drain contact. The first channel layer and the second channel layer are arranged above the first channel layer in a spaced apart manner over a substrate. The gate structure surrounds the first and second channel layers. The source/drain epitaxial structure is connected to the first and second channel layers. The source/drain contact is connected to the source/drain epitaxial structure. The second channel layer is closer to the source/drain contact than the first channel layer is to the source/drain contact, and the first channel layer is thicker than the second channel layer.

Abstract: An image sensor includes a pixel array and a logic circuit. The pixel array includes a pixel isolation layer between a plurality of pixels. Each of the plurality of pixels include a pixel circuit below at least one photodiode. The logic circuit acquires a pixel signal from the plurality of pixels. The pixel array includes at least one autofocusing pixel, which includes a first photodiode, a second photodiode, a pixel internal isolation layer between the first and second photodiodes, and a microlens on the first and second photodiodes. The pixel internal isolation layer includes a first pixel internal isolation layer and a second pixel internal isolation layer, separated from each other in a first direction, perpendicular to the upper surface of the substrate, and the first pixel internal isolation layer and the second pixel internal isolation layer include different materials.

Abstract: Devices, such as transistors, that use bismuth to create ohmic contacts are provided, as are methods of manufacturing the same. The transistors, such as field-effect transistors, can include one or more two-dimensional materials, and electrical contact areas can be created on the two-dimensional material(s) using bismuth. The bismuth can help to provide energy-barrier free, ohmic contacts, and the resulting devices can have performance levels that rival or exceed state-of-the-art devices that utilize three-dimensional materials, like silicon. The two-dimensional materials can include transition metal dichalcogenides, such as molybdenum disulfide.

Abstract: An HEMT includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer is different from the composition of the second III-V compound layer. A third III-V compound layer is disposed on the second III-V compound layer. The first III-V compound layer and the third III-V compound layer are composed of the same group III-V elements. The third III-V compound layer includes a body and numerous finger parts. Each of the finger parts is connected to the body. All finger parts are parallel to each other and do not contact each other. A source electrode, a drain electrode and a gate electrode are disposed on the first III-V compound layer.

Abstract: Various embodiments are disclosed for improved and structurally optimized transistors, such as RF power amplifier transistors. A transistor may include a drain metal portion raised from a surface of a substrate, a drain metal having a notched region, a gate manifold body with angled gate tabs extending from the gate manifold, and/or a source-connected shielding. The transistor may include a high-electron-mobility transistor (HEMT), a gallium nitride (GaN)-on-silicon transistor, a GaN-on-silicon-carbide transistor, or other type of transistor.

Abstract: A color control member includes a color control layer including a quantum dot and a color filter layer on the color control layer, wherein a low refractive layer may be between the color control layer and the color filter layer. The low refractive layer includes a base resin and a plurality of sets of hollow particles dispersed in the base resin, and each of the hollow particles of each set of the sets of hollow particles may have a spherical shape. The sets of hollow particles may have respective average diameters, and a ratio of two average diameters of the respective average diameters of the sets of hollow particles is about 2:1 to about 60:1, and the low refractive layer including the hollow particles may be formed through a continuous process at a low temperature.

Abstract: A semiconductor device having an active portion and a gate pad portion on a semiconductor substrate includes: a first semiconductor layer of a first conductivity type; and a second semiconductor layer of a second conductivity type. The active portion has: first semiconductor regions of the first conductivity type; a first electrode provided on the first semiconductor regions; and first trenches. The gate pad portion has: a gate electrode pad provided above the second semiconductor layer; second trenches provided beneath the gate electrode pad; and second semiconductor regions of the second conductivity type, each provided in the first semiconductor layer so as to be in contact with a respective one of bottoms of the second trenches. Each of the second trenches is continuous with a respective one of the first trenches. The second semiconductor layer is continuous from the active portion to the gate pad portion.

Abstract: A semiconductor device includes a base substrate. A first thin-film transistor is disposed on the base substrate. The first thin-film transistor includes a first input electrode, a first output electrode, a first semiconductor pattern disposed below a first insulating layer, and a first control electrode disposed on the first insulating layer and below a second insulating layer. A second thin-film transistor includes a second input electrode, a second output electrode, a second semiconductor pattern disposed on the second insulating layer, and a second control electrode disposed on an insulating pattern formed on the second semiconductor pattern and exposes a portion of the second semiconductor pattern. The first semiconductor pattern includes a crystalline semiconductor. The second semiconductor pattern incudes an oxide semiconductor. The first semiconductor pattern, the first control electrode, the second semiconductor pattern, and the second control electrode are overlapped.

Abstract: A transistor may include a buffer layer, source and drain contacts on the buffer layer, a barrier layer on the buffer layer, a conductive member on the barrier layer, a dielectric stack, and a gate metal. The barrier layer may be between the source and drain contacts. The conductive member may include a p-doped III-V compound. The dielectric stack may be on the barrier layer and on the conductive member. The dielectric stack may include a first dielectric layer and a second dielectric layer on the first dielectric layer. First and second trenches may extend through the dielectric stack to the conductive member and to the first dielectric layer, respectively. The gate metal may be on the dielectric stack, and may contact the conductive member through the first trench and may contact the first dielectric layer through the second trench.

Abstract: A silicon carbide MOSFET device that includes a silicon carbide substrate of a first dopant type; a first silicon carbide layer of the first dopant type on top of the silicon carbide substrate; a second silicon carbide layer of a second dopant type embedded in a top portion of the first silicon carbide layer; a third silicon carbide layer of the first dopant type embedded in a top portion of the second silicon carbide layer; a gate oxide layer overlapped to the first silicon carbide layer, the second silicon carbide layer and the third silicon carbide layer; and a fourth silicon carbide layer at least partially overlapping with the second silicon carbide layer along a direction normal to the silicon carbide substrate. The first silicon carbide layer has lower doping than the silicon carbide substrate and defines a drift region. The third silicon carbide layer has higher doping than the first silicon carbide layer.

Abstract: The present disclosure relates to a display substrate, a display panel and a display device. The display substrate includes: a base substrate including a display area and a peripheral area surrounding the display area; a common electrode located in the peripheral area and surrounding the display area; a panel crack detection line located in the peripheral area and surrounding the display area, wherein the panel crack detection line is located on one side of the common electrode away from the display area; and at least one electrostatic discharge circuit located in the peripheral area, wherein the at least one electrostatic discharge circuit includes at least one first thin film transistor including an active layer, a gate, a source and a drain, the source and the drain are electrically connected to the panel crack detection line, and the gate is electrically connected to the common electrode.