Abstract: A semiconductor device is provided, including a substrate, a seed layer on the substrate, an epitaxial layer on the seed layer, an electrode structure on the epitaxial layer and an electric field modulation structure. The electrode structure includes a gate structure, a source structure and a drain structure, wherein the source structure and the drain structure are positioned on opposite sides of the gate structure. The electric field modulation structure includes an electric connection structure and a conductive layer electrically connected to the electric connection structure. The conductive layer is positioned between the gate structure and the drain structure. The electric connection structure is electrically connected to the source structure and the drain structure.

Abstract: A semiconductor device includes a semiconductor layer that has a first main surface at one side and a second main surface at another side, a plurality of gate electrodes that are arranged at intervals on the first main surface of the semiconductor layer, an interlayer insulating film that is formed on the first main surface of the semiconductor layer such as to cover the gate electrodes, an electrode film that is formed on the interlayer insulating film, and a plurality of tungsten plugs that, between a pair of the gate electrodes that are mutually adjacent, are respectively embedded in a plurality of contact openings formed in the interlayer insulating film at intervals in a direction in which the pair of mutually adjacent gate electrodes face each other and each have a bottom portion contacting the semiconductor layer and a top portion contacting the electrode film.

Abstract: A lateral DMOS transistor structure includes a substrate of a first dopant polarity, a body region of the first dopant polarity, a source region, a drift region of a second dopant polarity, a drain region, a channel region, a gate structure over the channel region, a hybrid contact implant, of the second dopant polarity, in the source region, and a respective metal contact on or within each of the source region, gate structure, and drain region. The hybrid contact implant and the metal contact together form a hybrid contact defining first, second, and third electrical junctions. The first junction is a Schottky junction formed vertically between the source metal contact and the body. The second junction is an ohmic junction formed laterally between the source metal contact and the hybrid contact implant. The third junction is a rectifying PN junction between the hybrid contact implant and the channel region.

Abstract: A phase-change memory cell includes, in at least a first portion, a stack of at least one germanium layer covered by at least one layer made of a first alloy of germanium, antimony, and tellurium In a programmed state, resulting from heating a portion of the stack to a sufficient temperature, portions of layers of germanium and of the first alloy form a second alloy made up of germanium, antimony, and tellurium, where the second alloy has a higher germanium concentration than the first alloy.

Abstract: The present disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes a first III-nitride layer, a second III-nitride layer, a first contact layer, a second contact layer, a structure, and a gate layer. The second III-nitride layer is in direct contact with the first III-nitride layer. The first contact layer and the second contact layer are disposed over the second III-nitride layer. The structure is adjacent to an interface of the first III-nitride layer and the second III-nitride layer, and a material of the structure is different from a material of the first III-nitride layer or a material of the second III-nitride layer. The gate layer is disposed between the first contact layer and the second contact layer.

Abstract: A method of manufacturing one or more interconnects to magnetoresistive structure comprising (i) depositing a first conductive material in a via; (2) etching the first conductive material wherein, after etching the first conductive material a portion of the first conductive material remains in the via, (3) partially filling the via by depositing a second conductive material in the via and directly on the first conductive material in the via; (4) depositing a first electrode material in the via and directly on the second conductive material in the via; (5) polishing a first surface of the first electrode material wherein, after polishing, the first electrode material is (i) on the second conductive material in the via and (ii) over the portion of the first conductive material remaining in the via; and (6) forming a magnetoresistive structure over the first electrode material.

Abstract: Embodiments include a transistor and methods of forming a transistor. In an embodiment, the transistor comprises a semiconductor channel, a source electrode on a first side of the semiconductor channel, a drain electrode on a second side of the semiconductor channel, a polarization layer over the semiconductor channel, an insulator stack over the polarization layer, and a gate electrode over the semiconductor channel. In an embodiment, the gate electrode comprises a main body that passes through the insulator stack and the polarization layer, and a first field plate extending out laterally from the main body.

Abstract: A method of manufacturing a semiconductive structure includes receiving a first substrate; disposing an interconnection layer on the first substrate; forming a plurality of conductors over the interconnection layer; filing gaps between the plurality of conductors with a film; forming a barrier layer over the film; removing the barrier layer; and partially removing the film to expose a portion of the interconnection and leave a portion of the interconnection layer covered by the film.

Abstract: A high electron mobility transistor (HEMT) includes a channel layer, a plurality of barrier layers, and a p-type semiconductor layer. The barrier layers have an energy band gap greater than that of the channel layer. A gate electrode is arranged on the p-type semiconductor layer. A source electrode and a drain electrode are apart from the p-type semiconductor layer and the gate electrode on the barrier layers. Impurity concentrations of the barrier layers are different from each other in a drift area between the source electrode and the drain electrode.

Abstract: Embodiments of the present disclosure relate to a transfer head assembly and an LED transfer apparatus, and more particularly, to a transfer head assembly and an LED transfer apparatus in which a plurality of pickup units picks up LEDs, which are adhered to the upper surfaces of the LEDs, and transfers the LEDs to a display substrate. According to the embodiments of the present disclosure, a large number of LEDs located on a wafer substrate or a carrier substrate can be transferred in bulk to a display substrate. Thus, it is possible to rapidly perform the transfer process of the LEDs.

Abstract: A method is presented for enabling heat dissipation in resistive random access memory (RRAM) devices. The method includes forming a first thermal conducting layer over a bottom electrode, depositing a metal oxide liner over the first thermal conducting layer, forming a second thermal conducting layer over the metal oxide liner, recessing the second thermal conducting layer to expose the first thermal conducting layer, and forming a top electrode in direct contact with the first and second thermal conducting layers.

Abstract: A semiconductor device includes a switch element having a surface and first and second regions and including a first semiconductor material having a band-gap. The first region of the switch element is coupled to a source contact. A floating electrode has first and second ends. The first end of the floating electrode is coupled to the second region of the switch element. A voltage-support structure includes a second semiconductor material having a band-gap that is larger than the band-gap of the first semiconductor material. The voltage-support structure is in contact with the second end of the floating electrode. A drain contact is coupled to the voltage-support structure.

Abstract: Junction field effect transistors (JFETs) and related manufacturing methods are disclosed herein. A disclosed JFET includes a vertical channel region located in a mesa and a first channel control region located on a first side of the mesa. The first channel control region is at least one of a gate region and a first base region. The JEFT also includes a second base region located on a second side of the mesa and extending through the mesa to contact the vertical channel region. The vertical channel can be an implanted vertical channel. The vertical channel can be asymmetrically located in the mesa towards the first side of the mesa.

Abstract: Semiconductor devices is provided. The semiconductor device includes a semiconductor substrate having a first region and an adjacent second region; a plurality of adjacent first fins in the first region of the semiconductor substrate; a plurality of adjacent second fins in the second region of the semiconductor substrate; a first type of fin sidewall spacers; a second type of fin sidewall spacers; first doped layers formed between adjacent first type of fin sidewall spacers in the first region; and second doped layers formed between adjacent first type of fin sidewall spacers in the second region.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes a semiconductor substrate. A gate dielectric is disposed over the semiconductor substrate. A first source/drain region and a second source/drain region are disposed in the semiconductor substrate and on opposite sides of the gate dielectric. A gate electrode is disposed over the gate dielectric. A first dishing prevention structure is embedded in the gate electrode, where a perimeter of the first dishing prevention structure is disposed within a perimeter of the gate electrode.

Abstract: Aspects of the present inventive concept provide a semiconductor device capable of enhancing performance and reliability through source/drain engineering in a transistor including an oxide semiconductor layer. The semiconductor device includes a substrate, a metal oxide layer disposed on the substrate, a source/drain pattern being in contact with the metal oxide layer and including a portion protruding from a top surface of the metal oxide layer, a plurality of gate structures disposed on the metal oxide layer with the source/drain pattern interposed therebetween and each including gate spacers and an insulating material layer, the insulating material layer being in contact with the metal oxide layer, and not extending along a top surface of the source/drain pattern, and a contact disposed on the source/drain pattern, the contact being connected to the source/drain pattern.

Abstract: A lateral power semiconductor device structure comprises a pad-over-active topology wherein on-chip interconnect metallization and contact pad placement is optimized to reduce interconnect resistance. For a lateral GaN HEMT, wherein drain, source and gate finger electrodes extend between first and second edges of an active region, the source and drain buses run across the active region at positions intermediate the first and second edges of the active region, interconnecting first and second portions of the source fingers and drain fingers which extend laterally towards the first and second edges of the active region. External contact pads are placed on the source and drain buses. For a given die size, this interconnect structure reduces lengths of current paths in the source and drain metal interconnect, and provides, for example, at least one of lower interconnect resistance, increased current capability per unit active area, and increased active area usage per die.

Abstract: A method of manufacturing a semiconductor memory device and a semiconductor memory device, the method including providing a substrate that includes a cell array region and a peripheral circuit region; forming a mask pattern that covers the cell array region and exposes the peripheral circuit region; growing a semiconductor layer on the peripheral circuit region exposed by the mask pattern such that the semiconductor layer has a different lattice constant from the substrate; forming a buffer layer that covers the cell array region and exposes the semiconductor layer; forming a conductive layer that covers the buffer layer and the semiconductor layer; and patterning the conductive layer to form conductive lines on the cell array region and to form a gate electrode on the peripheral circuit region.

Abstract: Circuit-Under-Pad (CUP) device topologies for high-current lateral power switching devices are disclosed, in which the interconnect structure and pad placement are configured for reduced source and common source inductance. In an example topology for a power semiconductor device comprising a lateral GaN HEMT, the source bus runs across a centre of the active area, substantially centered between first and second extremities of source finger electrodes, with laterally extending tabs contacting the underlying source finger electrodes. The drain bus is spaced from the source bus and comprises laterally extending tabs contacting the underlying drain finger electrodes. The gate bus is centrally placed and runs adjacent the source bus. Preferably, the interconnect structure comprises a dedicated gate return bus to separate the gate drive loop from the power loop. Proposed CUP device structures provide for lower source and common source inductance and/or higher current carrying capability per unit device area.

Abstract: A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer of a first conductivity type; a second nitride semiconductor layer of a second conductivity type; an electron transport layer and an electron supply layer provided, in that order from a side on which the substrate is located, above the second nitride semiconductor layer and on an inner surface of a first opening; a gate electrode provided above the electron supply layer and covering the first opening; a source electrode provided in a second opening and connected to the second nitride semiconductor layer; a drain electrode; a third opening at an outermost edge part in a plan view of the substrate; and a potential fixing electrode provided in the third opening, the potential fixing electrode being connected to the second nitride semiconductor layer and in contact with neither the electron transport layer nor the electron supply layer.