Abstract: Disclosed is a display panel. The display panel includes a semiconductor structure; the semiconductor structure includes a substrate and a partition structure, disposed on the substrate and arranged to partition a film layer disposed on the substrate; the partition structure includes at least a base film layer and a partition film layer that are stacked in sequence; the partition film layer covers the base film layer, and at least one side of the partition film layer extends beyond a corresponding side of the base film layer; and the partition film layer warpage has a warpage structure located at an end portion thereof.

Abstract: A solid-state imaging device including: a semiconductor substrate having a first surface and a second surface opposed to each other, and including a photoelectric converter provided for each of pixel regions; an impurity diffusion region provided, for each of the pixel regions, in proximity to the first surface of the semiconductor substrate; and a contact electrode embedded in the semiconductor substrate from the first surface, and provided over and in contact with the impurity diffusion regions each provided for each of the pixel regions adjacent to each other.

Abstract: Embodiments of the disclosure generally provide methods of forming a capacitor layer or a gate insulating layer with high dielectric constant as well as low film current leakage and desired film qualities for display applications. In one embodiment, a thin film transistor structure includes a dielectric layer formed on a substrate, wherein the dielectric layer is a zirconium containing material comprising aluminum, and gate, source and drain electrodes formed on the substrate, wherein the gate, source and drain electrodes formed above or below the dielectric layer.

Abstract: A semiconductor manufacturing device including a polishing head that is capable of retaining a semiconductor substrate; a polishing pad having a processing surface to be abutted to the semiconductor substrate retained by the polishing head, the processing surface including a groove; a platen that is capable of rotating about a rotary shaft running along a direction intersecting the processing surface, in a state in which the polishing pad is retained by the platen; a measuring section that outputs a measurement value indicating a height of the processing surface at a predetermined location along a circumference of a circle centered about the rotary shaft of the platen; and a derivation section that derives a depth of the groove from the measurement value of the measuring section.

Abstract: A method for manufacturing a display module includes preparing a display module comprising a plurality of layers and forming a through-hole in the display module. The forming the through-hole includes performing a first irradiation process of irradiating a first laser beam along a first boundary defining the through-hole, performing a second irradiation process of irradiating a second laser beam along a second boundary after the first irradiation process, and performing a third irradiation process of irradiating a third laser beam along a third boundary after the second irradiation process. A time interval between the first irradiation process and the second irradiation process may be different from a time interval between the second irradiation process and the third irradiation process.

Abstract: Provided are a photoelectric chip, a manufacturing method and an installation method, which relate to the field of optical communication and transmission technologies. The chip is provided with a light-splitting groove (3), and the light-splitting groove (3) runs through an absorption layer (2) of the chip; the back of the chip is a light-entering side; the light-splitting groove (3) is configured to transmit and split out part (151) of incident light (15), and the other part (152) of the incident light (15) enters the absorption layer (2) for photovoltaic conversion. The photoelectric chip can split light and monitor optical power of the incident light.

Abstract: A method for manufacturing an optoelectronic device including the steps of forming a substrate having a support face; forming a first series of first areas adapted to the formation of all or part of light-emitting diodes, forming a second series of second areas on the support face, adapted to the formation of light confinement wall elements capable of forming a light confinement wall, the second areas defining therebetween sub-pixel areas; forming, from the first areas, light-emitting diodes; forming, by the same technique as in the previous step, from the second areas, light confinement wall elements, concomitantly with all or part of the light-emitting diodes which are formed in the previous step.

Abstract: The present disclosure relates to a semiconductor device with isolation and/or protection structures. A semiconductor device can include a substrate, a first transistor and a second transistor, wherein the first transistor and the second transistor are formed on the substrate, and an isolation structure formed on the substrate. The isolation structure can be formed on the substrate between the first transistor and the second transistor. The isolation structure can be configured to isolate the first transistor and the second transistor.

Abstract: In a disclosed semiconductor structure, a lateral bipolar junction transistor (BJT) has a base positioned laterally between a collector and an emitter. The base includes a semiconductor fin with a first portion that extends from a substrate through an isolation layer, a second portion on the first portion, and a third portion on the second portion. The collector and emitter are on the isolation layer and positioned laterally immediately adjacent to opposing sidewalls of the second portion of the semiconductor fin. In some embodiments, the BJT is a standard BJT where the semiconductor fin (i.e., the base), the collector, and the emitter are made of the same semiconductor material. In other embodiments, the BJT is a heterojunction bipolar transistor (HBT) where a section of the semiconductor fin (i.e., the base) is made of a different semiconductor material for improved performance. Also disclosed is a method of forming the structure.

Abstract: Embodiments of the present disclosure provide a method for forming a hole structure in a semiconductor device. The method for forming a hole structure having a first hole portion and a second hole portion connected to and over the first portion in a stack structure of a semiconductor device includes determining a hard mask layer. An etching resistivity of the hard mask layer may be inversely proportional to a difference between a first lateral dimension of the first hole portion and a second lateral dimension of the second hole portion, and the first lateral dimension may be less than the second lateral dimension. The method may also include forming the hard mask layer over the stack structure, and patterning the hard mask layer to form a first patterned hard mask layer that has a first mask opening. The first mask opening may have the first lateral dimension.

Abstract: Discussed is a light emitting display device which enables a common layer having high hole conductivity among common layers in respective stacks to include a material having a high orientation factor value so as to prevent generation of leakage current between subpixels and ensure high efficiency and a long lifespan.

Abstract: A tiled display device includes a first display panel including a first display area and a first non-display area adjacent to the first display area, and a second display panel including a second display area and a second non-display area between the second display area and the first non-display area. The first display panel includes a first lower substrate, emitting diodes disposed on the first lower substrate and overlapping the first display area, a first upper substrate including a lower surface facing the first lower substrate, a first black matrix pattern disposed on the lower surface of the first upper substrate and overlapping the first non-display area, and a first photochromic matrix pattern disposed on the lower surface of the first upper substrate, overlapping the first non-display area, and transmitting light.

Abstract: A mask-integrated surface protective tape, which has at least a substrate film and a mask material layer, wherein the mask material layer is provided directly on the substrate film, or is provided on the substrate film through a temporary-adhesive layer, and wherein a parallel ray transmittance of the mask material layer at a wavelength region of 355 nm is 30% or less; and a method of producing a semiconductor chip.

Abstract: A method for manufacturing a display device including a light-emitting element, the method includes: storing, in a manufacturing process of the display device, a plurality of abutting positions where a back face of a support substrate locally abuts a manufacturing apparatus; forming, on a surface of the support substrate on a side on which the light-emitting element is to be formed, a peeling layer at a position opposing at least one position of the plurality of abutting positions stored; forming, on the support substrate, a resin layer to cover the peeling layer; forming a TFT layer on the resin layer; forming the light-emitting element on the TFT layer; and peeling the support substrate and the resin layer.

Abstract: A semiconductor package is provided. The semiconductor package includes a heat dissipation substrate including a first conductive through-via embedded therein; a sensor die disposed on the heat dissipation substrate; an insulating encapsulant laterally encapsulating the sensor die; a second conductive through-via penetrating through the insulating encapsulant; and a first redistribution structure and a second redistribution structure disposed on opposite sides of the heat dissipation substrate. The second conductive through-via is in contact with the first conductive through-via. The sensor die is located between the second redistribution structure and the heat dissipation substrate. The second redistribution structure has a window allowing a sensing region of the sensor die receiving light. The first redistribution structure is electrically connected to the sensor die through the first conductive through-via, the second conductive through-via and the second redistribution structure.

Abstract: A gate structure includes a gate dielectric layer, a work function layer, a metal layer, and a barrier layer. The work function layer is surrounded by the gate dielectric layer. The metal layer is disposed over the work function layer. The barrier layer is surrounded by the work function layer and surrounds the metal layer. The barrier layer includes fluorine and silicon, or fluorine and aluminum. The barrier layer is a tri-layered structure.

Abstract: A semiconductor device includes a silicon substrate; a semiconductor fin over the silicon substrate; and an isolation structure over the silicon substrate. The semiconductor fin includes a first portion and a second portion over the first portion. The first portion is surrounded by the isolation structure, and the second portion protrudes above the isolation structure. The second portion has a different crystalline lattice constant than the first portion. The first portion includes a first dopant, and the second portion is substantially free of the first dopant. The semiconductor device further includes a gate structure above the isolation structure and engaging multiple surfaces of the second portion.

Abstract: The present invention provides a photodiode and a display screen. The photodiode includes a first electrode and a second electrode in order. When a direction of an incident light of the photodiode is a first direction, a material of the first electrode is a transparent conductive material, and a material of the second electrode is a metal material. When the direction of the incident light of the photodiode is a second direction, the second electrode is made of a transparent conductive material, and the first electrode is made of a metal material.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device having self-aligned isolation structures. The present disclosure provides self-aligned isolation fins that can be formed by depositing dielectric material in openings formed in a spacing layer or by replacing portions of fins with dielectric material. The self-aligned isolation fins can be separated from each other by a critical dimension of the utilized photolithography process. The separation between self-aligned isolation fins or between the self-aligned isolation fins and active fins can be approximately equal to or larger than the separations of the active fins.

Abstract: An image sensor includes: a substrate including a first surface and a second surface on which light is incident, the second surface being opposite to the first surface; a photoelectric converter provided in the substrate; a first metal layer provided on the first surface of the substrate; a second metal layer provided on the first metal layer; and a capacitor layer provided between the first metal layer and the second metal layer, wherein the capacitor layer includes: a first lower electrode electrically connected to the first metal layer, a first upper electrode electrically connected to the second metal layer, a second upper electrode spaced apart from the first upper electrode and electrically connected to the second metal layer, a first capacitor provided between the first lower electrode and the first upper electrode, and a second capacitor provided between the first lower electrode and the second upper electrode.