Abstract: Provided is a solid-state imaging element, a manufacturing method, and an electronic apparatus which are capable of further improving a light-blocking effect. The solid-state imaging element has a laminated structure in which a memory substrate, a logic substrate, and a sensor substrate are laminated. The solid-state imaging element includes a through electrode that connects the memory substrate and the sensor substrate in a manner passing through a semiconductor layer of the logic substrate, and a light-blocking metal film arranged in a wiring layer included in the logic substrate and provided on the sensor substrate side, where the light-blocking metal film has an opening opened so as to allow the through electrode to pass through. The solid-state imaging element further includes a contact electrode formed on a bonded surface between the logic substrate and the sensor substrate and used to connect the through electrode to the sensor substrate side.

Abstract: An organic light-emitting diode display panel, a manufacturing method of an organic light-emitting diode display panel and a display device are provided. The organic light-emitting diode display panel includes: a substrate; a pixel definition layer, located on the substrate; and an encapsulation layer, located on the pixel definition layer, a desiccant is added to at least one of the pixel definition layer and the encapsulation layer.

Abstract: A method for forming a semiconductor device comprises receiving a structure having a substrate, an isolation structure over the substrate, and a fin over the substrate and adjacent to the isolation structure. The method further includes etching a portion of the fin, resulting in a trench, forming a doped material layer over bottom and sidewalls of the trench, and growing at least one epitaxial layer over the doped material layer in the trench. The method further includes recessing the isolation structure and the doped material layer, leaving a first portion of the at least one epitaxial layer surrounded by the doped material layer and performing an annealing process, thereby driving dopants from the doped material layer into the first portion.

Abstract: Provided are integrated circuit packages and methods of forming the same. An integrated circuit package includes an integrated circuit structure, a first die stack and a dummy die. The first die stack includes a plurality of first die structures and is bonded to the integrated circuit structure at a first side of the first die stack. The dummy die includes a plurality of through substrate vias, is located aside the first die stack and is electrically connected to the integrated circuit structure at the first side of the first die stack. In some embodiments, the height of the through substrate vias of the dummy die is the same as the height of the first die stack.

Abstract: A chip carrier socket for an electronic-photonic integrated-circuit (EPIC) assembly comprises a carrier bottom and a carrier top configured to mate to the carrier bottom while enclosing the EPIC assembly within an enclosed cavity. The carrier bottom comprises one or more conductive vias passing from a first surface of the carrier bottom to an opposite second surface of the carrier bottom, each conductive via providing electrical connectivity between an electrically conductive pad on the first surface of the carrier bottom and a respective electrically conductive pad, solder ball, or electrically conductive spring on the second surface of the carrier bottom. One or both of the carrier bottom and the carrier top comprises a fluid inlet port and a fluid outlet port. Further, either or both of the carrier bottom and the bottom top comprises an optical via passing from one surface to another of the carrier bottom or carrier top.

Abstract: A method for inspecting a surface of a wafer, includes steps of: irradiating a surface of the wafer with a laser beam having three or more distinct wavelengths; detecting a reflected light from the surface of the wafer when the surface of the wafer is irradiated with the laser beam; and determining whether a foreign matter exists on the surface of the wafer based on reflectances of the surface of the wafer with respect to the laser beam having the three or more distinct wavelengths, wherein the step of determining whether the foreign matter exists includes a step of determining whether the foreign matter is a metal or a non-metal.

Abstract: A method of manufacturing a semiconductor device includes forming a lower mold having lower layers stacked on a substrate and lower channel structures passing therethrough; forming an upper mold including upper layers stacked on the lower mold and upper channel structures passing therethrough; removing the upper mold to expose an upper surface of the lower mold; separating an upper original image in which traces of the upper channel structures are displayed, and a lower original image in which the lower channel structures are displayed, from an original image capturing the upper surface of the lower mold; inputting the upper original image into a learned neural network to acquire an upper restored image in which cross sections of the upper channel structures are displayed; and comparing the upper restored image with the lower original image to verify an alignment state of the upper and lower molds.

Abstract: A spin orbit memory device includes a material layer stack on a spin orbit electrode. The material layer stack includes a magnetic tunnel junction (MTJ) and a synthetic antiferromagnetic (SAF) structure on the MTJ. The SAF structure includes a first magnet structure and a second magnet structure separated by an antiferromagnetic coupling layer. The first magnet structure includes a first magnet and a second magnet separated by a single layer of a non-magnetic material such as platinum. The second magnet structure includes a stack of bilayers, where each bilayer includes a layer of platinum on a layer of a magnetic material such.

Abstract: A photoelectric conversion device includes a first electrode and a second electrode facing each other, a photoelectric conversion layer between the first electrode and the second electrode and configured to absorb light in at least one part of a wavelength spectrum of light and to convert it into an electric signal, and an organic auxiliary layer between the first electrode and the photoelectric conversion layer and having a higher charge mobility than a charge mobility of the photoelectric conversion layer. An organic sensor may include the photoelectric conversion device. An electronic device may include the organic sensor.

Abstract: Disclosed is a metal source/drain-based field effect transistor having a structure that replaces a portion of a semiconductor of a source/drain with a metal and a method of manufacturing the same. By replacing the source/drain region with the source/drain metal region, increase of the parasitic resistance of a conventional three-dimensional MOSFET of several tens of nanometers, lattice mismatch of the source/drain during selective epitaxial growth, and self-heating effect can be fundamentally solved. Further, since the metal is deposited after the partial etching of the source/drain region or the selective epitaxial growth is partially performed under the conventional CMOS process, the process can be performed without using any additional mask.

Abstract: This disclosure pertains to the field of nanotechnology. The disclosure provides nanostructure compositions comprising (a) at least one population of nanostructures; (b) at least one metal halide bound to the surface of the nanostructures; and (c) at least one metal carboxylate bound to the surface of the nanostructures. The nanostructure compositions have high quantum yield, narrow emission peak width, tunable emission wavelength, and colloidal stability. Also provided are methods of preparing the nanostructure compositions. And, nanostructure films and molded articles comprising the nanostructure compositions are also provided.

Abstract: A bonding structure includes a first layer of first alloy component disposed on a substrate and a first layer of a second alloy component disposed on the first alloy component. The second alloy component has a lower melting temperature than the first alloy component. A second layer of the first alloy component is disposed on the first layer of the second alloy component and a second layer of the second alloy component is disposed on the second layer of the first alloy component.

Abstract: A method for manufacturing a display module includes preparing a display module comprising a plurality of layers and forming a through-hole in the display module. The forming the through-hole includes performing a first irradiation process of irradiating a first laser beam along a first boundary defining the through-hole, performing a second irradiation process of irradiating a second laser beam along a second boundary after the first irradiation process, and performing a third irradiation process of irradiating a third laser beam along a third boundary after the second irradiation process. A time interval between the first irradiation process and the second irradiation process may be different from a time interval between the second irradiation process and the third irradiation process.

Abstract: Provided is a method of producing semiconductor nanoparticles that exhibit a band-edge emission, and are superior in quantum yield. The method includes raising the temperature of a first mixture containing a silver (Ag) salt, a salt containing at least one of indium (In) and gallium (Ga), a solid compound that serves as a supply source of sulfur (S), and an organic solvent to a temperature in a range of from 125° C. to 175° C., and heat-treating, subsequent to the raising of the temperature, the first mixture at a temperature in a range of from 125° C. to 175° C. for three seconds or more to obtain a solution containing semiconductor nanoparticles, and decreasing the temperature of the solution containing semiconductor nanoparticles. The solid compound that serves as a supply source of S contains thiourea.

Abstract: A method for forming FinFETs comprises forming a plurality of first fins and a plurality of second fins over a substrate and embedded in isolation regions, depositing a first photoresist layer over the substrate, removing the first photoresist layer over an n-type region, applying a first ion implantation process to the first isolation regions, wherein dopants with a first polarity type are implanted in the first isolation regions, depositing a second photoresist layer over the substrate, removing the second photoresist layer over a p-type region, applying a second ion implantation process to the second isolation regions, wherein dopants with a second polarity type are implanted in the second isolation regions, applying an annealing process to the isolation regions and recessing the first isolation regions and the second isolation regions through an etching process.

Abstract: A method includes forming a through-via from a first conductive pad of a first device die. The first conductive pad is at a top surface of the first device die. A second device die is adhered to the top surface of the first device die. The second device die has a surface conductive feature. The second device die and the through-via are encapsulated in an encapsulating material. The encapsulating material is planarized to reveal the through-via and the surface conductive feature. Redistribution lines are formed over and electrically coupled to the through-via and the surface conductive feature.

Abstract: A method for developing an enhancement model for low-quality visual data, the method comprising the steps of receiving one or more sections of higher-quality visual data; and training a hierarchical algorithm. The hierarchical algorithm is operable to increase the quality of one or more sections of lower-quality visual data so as to substantially reproduce the one or more sections of higher-quality visual data. The hierarchical algorithm is then outputted.

Abstract: A method for fabricating a semiconductor device includes forming a first line pattern within sacrificial mandrel material disposed on at least one hard mask layer disposed on a substrate. The first line pattern has a pitch defined by a target line width and a minimum width of space between lines. The method further includes forming, within the first line pattern, a first spacer having a width corresponding to the minimum width of space between lines to minimize pinch points and a first gap having the target line width, and forming a first plug within the first gap corresponding to a first location above the at least one hard mask layer to block pattern transfer into the at least one hard mask layer.

Abstract: A display screen, comprising a panel (1), a light-emitting plate (2), a light blocking film (3) and an image sensor (4) that are stacked sequentially.

Abstract: A capacitor that includes a substrate having a first principal surface and a second principal surface, a lower electrode on the first principal surface, a dielectric film on the lower electrode, and an upper electrode on the dielectric film, wherein at least one of the lower electrode and the upper electrode has, in plan view of the first principal surface, a first region having a rectangular shape, and at least one second region protruding from at least one side of the first region.