Abstract: A semiconductor structure and a method of fabricating the same is disclosed. The semiconductor device includes a conductive structure that comprises: an upper conductive line arranged above and in electrical connection with a circuit component in a lower device layer through a via plug, wherein the upper conductive line extends laterally over the via plug; an interposing layer having a substantially uniform thickness arranged between the via plug and the upper conductive line, and extending laterally beyond a planar projection of the via plug, wherein the upper conductive line is in electrical connection with the via plug through the interposing layer; and an overlayer is disposed over the upper conductive line.

Abstract: The present embodiment provide a method for evaluating anion permeability of a graphene-containing membrane and also to provide a photoelectric conversion device employing a graphene-containing membrane having controlled anion permeability.

Abstract: In a transistor including an oxide semiconductor layer, an oxide insulating layer is formed so as to be in contact with the oxide semiconductor layer. Then, oxygen is introduced (added) to the oxide semiconductor layer through the oxide insulating layer, and heat treatment is performed. Through these steps of oxygen introduction and heat treatment, impurities such as hydrogen, moisture, a hydroxyl group, or hydride are intentionally removed from the oxide semiconductor layer, so that the oxide semiconductor layer is highly purified.

Abstract: A method for forming an epitaxial source/drain structure in a semiconductor device includes providing a substrate having a plurality of fins extending from the substrate. In some embodiments, a liner layer is formed over the plurality of fins. The liner layer is patterned to expose a first group of fins of the plurality of fins in a first region. In some embodiments, a first epitaxial layer is formed over the exposed first group of fins and a barrier layer is formed over the first epitaxial layer. Thereafter, the patterned liner layer may be removed. In various examples, a second epitaxial layer is selectively formed over a second group of fins of the plurality of fins in a second region.

Abstract: An integrated circuit chip includes a front face having an electrical connection pad. An overmolded encapsulation block encapsulates the integrated circuit chip and includes a front layer at least partially covering a front face of the integrated circuit chip. A through-hole the encapsulation block is located above the electrical connection pad of the integrated circuit chip. A wall of the through-hole is covered with an inner metal layer that is joined to the front pad of the integrated circuit chip. A front metal layer covers a local zone of the front face of the front layer, with the front metal layer being joined to the inner metal layer to form an electrical connection. The inner metal layer and the front metal layer are attached or anchored to activated additive particles that are included in the material of the encapsulation block.

Abstract: An Integrated Circuit (IC) assembly, comprising an IC package coupled to a substrate, and a subassembly comprising a thermal interface layer. The thermal interface layer comprises a phase change material (PCM) over the IC package. At least one thermoelectric cooling (TEC) apparatus is thermally coupled to the thermal interface layer.

Abstract: A display device includes a planarization layer disposed on a substrate, a first electrode disposed on the planarization layer and including silver (Ag), a contact preventing layer disposed on the first electrode, including a light absorbing material, and including a top surface and a side surface extending from an end of the top surface, and a pixel defining layer disposed on the contact preventing layer and including a bottom surface facing the top surface of the contact preventing layer, and a side surface extending from an end of the bottom surface. The first electrode includes a first region overlapping pixel defining layer. The contact preventing layer includes a second region overlapping the first region between the first electrode and the pixel defining layer. A first edge where the top and side surfaces of the contact preventing layer meet is located on the bottom surface of the pixel defining layer.

Abstract: An object of one embodiment of the present invention is to provide a multicolor light-emitting element that utilizes fluorescence and phosphorescence and is advantageous for practical application. The light-emitting element has a stacked-layer structure of a first light-emitting layer containing a host material and a fluorescent substance, a separation layer containing a substance having a hole-transport property and a substance having an electron-transport property, and a second light-emitting layer containing two kinds of organic compounds that form an exciplex and a substance that can convert triplet excitation energy into luminescence. Note that a light-emitting element in which light emitted from the first light-emitting layer has an emission spectrum peak on the shorter wavelength side than an emission spectrum peak of the second light-emitting layer is more effective.

Abstract: Provided is a semiconductor module including semiconductor devices and a cooling apparatus, wherein the semiconductor device has semiconductor chips and a circuit board with the semiconductor chips implemented thereon; the cooling apparatus has a top plate, a side wall, a bottom plate, a coolant flow portion, an inlet, an outlet and a plurality of fins; the top plate and the bottom plate have three through holes that are through holes for inserting fastening members that fasten the semiconductor module to an external apparatus, penetrating the top plate and the bottom plate in one direction respectively; and a geometric center of gravity of a aperture of at least one of the inlet and the outlet may also be positioned inside a virtual triangle with the three through holes being vertexes in planar view.

Abstract: The present application discloses a method for fabricating a semiconductor device. The method for fabricating a semiconductor device includes providing a substrate, forming a pad structure above the substrate, and forming a top groove on a top surface of the pad structure.

Abstract: The display substrate may include a base substrate, a plurality of sub-pixels in an array on the base substrate, an isolation layer on a side of a second electrode layer opposite from the light-emitting layer, and an auxiliary conductive layer on a side of the isolation layer opposite from the second electrode layer. The isolation layer may comprise via openings, orthographic projection of each of the via openings on the base substrate may substantially overlap with orthographic projection of the pixel defining layer on the base substrate, and the auxiliary conductive layer may be connected to the second electrode layer through the via openings.

Abstract: One or more embodiments include a display apparatus including an opening, an apparatus for manufacturing the display apparatus, and a method of manufacturing the display apparatus capable of reducing generation of gas or foreign matter.

Abstract: A thermoelectric material element includes: a thermoelectric material portion composed of a thermoelectric material that includes a first crystal phase and a second crystal phase during an operation, the second crystal phase being different from the first crystal phase; a first electrode disposed in contact with the thermoelectric material portion; and a second electrode disposed in contact with the thermoelectric material portion and disposed to be separated from the first electrode. During the operation, the thermoelectric material portion includes a first temperature region having a first temperature, and a second temperature region having a second temperature lower than the first temperature of the first temperature region. A ratio of the first crystal phase to the second crystal phase in the first temperature region is larger than a ratio of the first crystal phase to the second crystal phase in the second temperature region.

Abstract: Disclosed are a quantum dot display panel, a manufacturing method thereof and a display device. The manufacturing method includes: forming a first functional layer on a substrate; processing the first functional layer so that the first functional layer includes a processed region and the processed region includes ions having a first polarity; forming a quantum dot layer having a second polarity in the processed region. The second polarity and the first polarity are opposite electrical polarities.

Abstract: Provided is a solid-state imaging element, a manufacturing method, and an electronic apparatus which are capable of further improving a light-blocking effect. The solid-state imaging element has a laminated structure in which a memory substrate, a logic substrate, and a sensor substrate are laminated. The solid-state imaging element includes a through electrode that connects the memory substrate and the sensor substrate in a manner passing through a semiconductor layer of the logic substrate, and a light-blocking metal film arranged in a wiring layer included in the logic substrate and provided on the sensor substrate side, where the light-blocking metal film has an opening opened so as to allow the through electrode to pass through. The solid-state imaging element further includes a contact electrode formed on a bonded surface between the logic substrate and the sensor substrate and used to connect the through electrode to the sensor substrate side.

Abstract: An organic light-emitting diode display panel, a manufacturing method of an organic light-emitting diode display panel and a display device are provided. The organic light-emitting diode display panel includes: a substrate; a pixel definition layer, located on the substrate; and an encapsulation layer, located on the pixel definition layer, a desiccant is added to at least one of the pixel definition layer and the encapsulation layer.

Abstract: A method for forming a semiconductor device comprises receiving a structure having a substrate, an isolation structure over the substrate, and a fin over the substrate and adjacent to the isolation structure. The method further includes etching a portion of the fin, resulting in a trench, forming a doped material layer over bottom and sidewalls of the trench, and growing at least one epitaxial layer over the doped material layer in the trench. The method further includes recessing the isolation structure and the doped material layer, leaving a first portion of the at least one epitaxial layer surrounded by the doped material layer and performing an annealing process, thereby driving dopants from the doped material layer into the first portion.

Abstract: Provided are integrated circuit packages and methods of forming the same. An integrated circuit package includes an integrated circuit structure, a first die stack and a dummy die. The first die stack includes a plurality of first die structures and is bonded to the integrated circuit structure at a first side of the first die stack. The dummy die includes a plurality of through substrate vias, is located aside the first die stack and is electrically connected to the integrated circuit structure at the first side of the first die stack. In some embodiments, the height of the through substrate vias of the dummy die is the same as the height of the first die stack.

Abstract: A chip carrier socket for an electronic-photonic integrated-circuit (EPIC) assembly comprises a carrier bottom and a carrier top configured to mate to the carrier bottom while enclosing the EPIC assembly within an enclosed cavity. The carrier bottom comprises one or more conductive vias passing from a first surface of the carrier bottom to an opposite second surface of the carrier bottom, each conductive via providing electrical connectivity between an electrically conductive pad on the first surface of the carrier bottom and a respective electrically conductive pad, solder ball, or electrically conductive spring on the second surface of the carrier bottom. One or both of the carrier bottom and the carrier top comprises a fluid inlet port and a fluid outlet port. Further, either or both of the carrier bottom and the bottom top comprises an optical via passing from one surface to another of the carrier bottom or carrier top.

Abstract: A method for inspecting a surface of a wafer, includes steps of: irradiating a surface of the wafer with a laser beam having three or more distinct wavelengths; detecting a reflected light from the surface of the wafer when the surface of the wafer is irradiated with the laser beam; and determining whether a foreign matter exists on the surface of the wafer based on reflectances of the surface of the wafer with respect to the laser beam having the three or more distinct wavelengths, wherein the step of determining whether the foreign matter exists includes a step of determining whether the foreign matter is a metal or a non-metal.