Abstract: The Multicore Bus Architecture (MBA) protocol includes a novel technique of sharing the same physical channel for all transaction types. Two channels, the Transaction Attribute Channel (TAC) and the Transaction Data Channel (TDC) are used. The attribute channel transmits bus transaction attribute information optionally including a transaction type signal, a transaction ID, a valid signal, a bus agent ID signal, an address signal, a transaction size signal, a credit spend signal and a credit return signal. The data channel connected a data subset of the signal lines of the bus separate from the attribute subset of signal lines the bus. The data channel optionally transmits a data valid signal, a transaction ID signal, a bus agent ID signal and a last data signal to mark the last data of a current bus transaction.

Abstract: In an example, a method for transmitting data includes determining, at a Universal Serial Bus (USB) host, a USB data transfer type of USB data being transmitted from the host device to a USB device, and determining a priority of the USB data based on the determined USB data transfer type. The example method also includes controlling transfer of the USB data from a protocol adaptation layer (PAL) of the USB host to a network layer of the USB host based on the determined priority.

Abstract: Providing I/O operations to a storage device includes selecting a portion of original I/O operations based on a first set of criteria, determining whether to subdivide each of the portion of original I/O operations that are selected according to a second set of criteria different than the first set of criteria, and converting each of the original I/O operations selected for subdivision into a plurality of subdivided I/O operations for different portions of data for a corresponding one of the original I/O operations, where at least two of the different portions are from a single track of data on the storage device. The first set of criteria may include whether the I/O operations are for multiple tracks of data and whether the storage device supports subdividing a single track. The second set of criteria may include determining a measured amount of performance improvement for previous subdivision operations.

Abstract: Systems, apparatuses, and methods for coalescing interrupts temporally for later processing are described. An interrupt controller in a computing system maintains a timer for tracking an amount of time remaining after receiving an interrupt before a processor is awakened to service the interrupt. For a received interrupt with a latency tolerance greater than a threshold, the interrupt controller compares a value currently stored in the timer and the latency tolerance selected based on class. The smaller value is retained in the timer. When the timer expires, the interrupt controller sends wakeup indications to one or more processors and indications of the waiting interrupts.

Abstract: A modified serial peripheral interface (SPI) is provided in each of a master device and a plurality of slave devices that does not use a slave select line. The master device may thus engage in full-duplex serial communication with each slave device through an SPI MOSI line, an SPI MISO line, and an SPI clock line.

Abstract: Discovery of electronic devices utilizing a control bus. An embodiment of a method includes connecting a receiving device to a cable, where the cable includes a control bus. If the receiving device is in a disconnect state and a signal from a transmitting device is detected on the control bus, the device is transferred to a state for a first type of transmitting device. If the receiving device is in either the disconnect state or the state for the first type of transmitting device and a predetermined voltage signal is received from the transmitting device, then the receiving device is transferred to a state for a second type of transmitting device.

Abstract: A buffer control system for a data storage device controller comprises a command module and a burst module. The command module receives first channel data from a first channel having a first data format and second channel data from a second channel having a second data format and converts the first channel data and the second channel data to respective data packets each having a third data format that is different than the first data format and the second data format. The burst module that selectively transmits the data packets having the third data format to a memory in a single write burst.

Abstract: An architecture and method in an integrated circuit for configuring a controller to facilitate communication with a plurality of external device interfaces. The integrated circuit includes a processor, a first memory, a second memory, including a plurality of dedicated memory blocks containing configuration data, and a plurality of external device interfaces. The processor is configured to write a microcode instruction to the first memory. The controller is configured to read the microcode instruction in the first memory and as a result access one of the plurality of dedicated memory blocks. Next, the controller processes the configuration data in the dedicated memory block according to the microcode instruction. As a result, the controller is configured to communicate with one of the plurality of external device interfaces. This process may be repeated as needed to configure the controller to communicate with different device interfaces using different communication protocols.

Abstract: A connection device for selecting an optimum receiver includes a single first port, in which a transmitter is connected via a bidirectional type cable, and a plurality of second ports, in which a plurality of receivers are connected via respective bidirectional type cables. The connection device further includes a transmission control unit which acquires transmitter function information from the transmitter via the first port as well as acquiring receiver function information from each of the plurality of receivers via their respective second ports. A transmission control unit links together the first port and the respective second port from among the plurality of second ports, which is connected to the receiver which is endowed with receiver function information closest to the transmitter function information.

Abstract: Embodiments of the present invention provide an interface device and method for command processing for commands requiring data flow in both directions on a Fiber Channel or other data transport protocol exchange. The commands can include proprietary commands, SCSI linked commands or other commands known in the art. According to one embodiment, and interface device can assign a command a data flow direction indicator. When a reply to the command is received, the interface device can determine if the reply is expected or unexpected based on the data flow direction specified by the data flow direction indicator. If the reply is unexpected, the interface device can determine whether to process the reply. According to one embodiment, the data flow direction indicator can be the exchange identification.

Abstract: There is disclosed an operand queue for use in a floating point unit. The floating point unit comprises floating point processing units for executing floating point instructions that write operands to an external memory and for executing floating point instructions that read operands from the external memory. The floating point also comprises an operand queue for storing a plurality of operands associated with one or more operations being processed in the floating point unit. The operand queue stores a first operand being written to an external memory by a floating point write instruction executed by a first one of the plurality of floating point processing units and supplies the first operand to a floating point read instruction executed by a second one of the plurality of floating point processing units subsequent to the execution of the floating point write instruction.

Abstract: A data generator provides faster data than before. A parallel data generator 18 provides first data having four or five effective data width according to a divided clock DCLK. A bit width adjuster 20 having a FIFO memory receives the first parallel data to provide second parallel data of constant four bit width despite of the bit width of the first parallel data. A parallel to serial converter 12 converts the second parallel data into serial data according to a reference clock RCLK that is faster than divided clock DCLK. The frequency of the divided clock DCLK can be constant, which makes it possible to use DLL to fasten the operation of the logic circuits.

Abstract: A method for communicating video data between at least a first host and a second host comprises: identifying, at a server, an address of the first host, to which the second host may communicate video data, and a sequence number expected by a network security system coupled between the first host and the server; and communicating, from the second host to the first host, video data using the address of the first host and the sequence number expected. The method may further comprise: identifying, at the server, an address of the second host, to which the first host may communicate video data, and a second sequence number expected by a network security system coupled between the second host and the server; and communicating, from the first host to the second host, video data using the address of the second host and the second expected sequence number. The second host may be adapted to perform the act of communicating without use of an intermediate server.

Abstract: Enabling virtualization in a SAS expander is disclosed. For each SAS address to be virtualized through one or more physical or virtual Phy, a reference Phy associated with each SAS address is created within the expander. Next, a route table is generated that includes an entry for each of the SAS addresses being virtualized, each entry associated with one or more of the physical or virtual Phy through which the SAS address is being virtualized. With the route table so established, requests for a virtualized SAS address are routed to a particular one of the one or more physical or virtual Phy associated with the virtualized SAS address in the route table.

Abstract: A compute unit with an internal bit FIFO circuit includes at least one data register, a lookup table, a configuration register including FIFO base address, length and read/write mode fields for configuring a portion of the lookup table as a bit FIFO circuit and a read/write pointer register responsive to an instruction having a lookup table identification field, length of bits field and register extract/deposit field for selectively transferring in a single cycle between the FIFO circuit and the data register a bit field of specified length.

Abstract: An apparatus and method for operating many applications between a portable storage device and a digital device are provided. The method includes opening at least two logical channels from the digital device to the portable storage device through a physical channel, transmitting and receiving data between a plurality of applications of the digital device and a plurality of applications of the portable storage device through the opened logical channels, and closing the logical channels after finishing the transmitting and receiving of the data.

Abstract: An apparatus and a computer program product are provided for completing a plurality of (direct memory access) DMA commands in a computer system. It is determined whether the DMA commands are chained together as a list DMA command. Upon a determination that the DMA commands are chained together as a list DMA command, it is also determined whether a current list element of the list DMA command is fenced. Upon a determination that the current list element is not fenced, a next list element is fetched and processed before the current list element has been completed.

Abstract: Configuration information settings for a storage device are made highly reliable and facilitated. The storage device includes a service processor for setting storage device configuration information, and a terminal device connected to the service processor via a private line to send a command group, received from an operator and related to the storage device configuration information, to the service processor. The service processor also includes a device for determining approval or denial of execution of the command group prior to execution of the command group received from the terminal device.

Abstract: A method and apparatus for managing data to be stored in a memory of a portable device, and a user interface method using the same. The method includes generating a virtual device for the portable device in a storage unit of a data management apparatus; storing information on at least one content file, which is used to transmit the at least one content file to the virtual device, in the virtual device; and if the portable device is connected to the data management apparatus, synchronizing the portable device with the virtual device by transmitting the at least one content file to the portable device with reference to the information stored in the virtual device.

Abstract: A first connection is established between a first device and a host, wherein the first device is host-capable. A second connection is established between a second device and the host. Proxy association is performed between the first device and the second device by the host to associate the first and second devices, wherein the first and second devices are unable to directly associate, wherein the host passes association information between the first and second devices.