Abstract: This invention relates to a method, system and computer program product for reading data from a storage controller in storage area network. A read data instruction is received from an application requesting data from the storage controller using a primary data path. If the data on the primary data path is not transferred in a defined time interval using the primary data path, data is requested from the storage controller using one or more alternative data paths. Data is received from the storage controller on one of data paths and into a buffer. When the read instruction has completed and that the data is in the buffer, the application is notified. Each data path is associated with a buffer and the data is received into a buffer associated with the path. The application is informed which buffer holds the data and the application accesses the data from this buffer.

Abstract: A multi function device includes a main board configured to control functions corresponding to a model of the multi function device and a sub board configured to be connected with the main board. The sub board carries out peripheral control corresponding to the model of the multi function device. Main board first identification information indicative of a category of the main board is obtained, and main board second identification information intrinsic to each model of the multi function device is also obtained. Then, the model of the multi function device is identified based on the main board first identification information and the main board second identification information when the multi function device is powered on. Further, function information corresponding to the identified model is obtained. The main board and the sub board of the multi function device are controlled based on the function information so as to function correctly.

Abstract: System and method for automatically updating a memory map coupled to or included in a programmable controller (PrC). A PrC may automatically detect at least one programmable hardware element (PHE) coupled to the PrC. The PHE may provide a customizable interface, i.e., input and output (I/O) interface, between one or more devices and the PrC. The devices may include one or more measurement, data acquisition, signal generation, automation, motion control, and/or analysis device(s), among others. The PHE may perform one or more functions on the data transmitted between the device(s) and the PrC. One or more of the PHEs and/or device(s) may be local or remote to the PrC. The PrC may automatically update the memory map based on a hardware I/O interface of the at least one programmable hardware element, where the memory map facilitates communications between programs executing on the PrC and the programmable hardware element.

Abstract: A data output apparatus checks data accumulated state in the accumulating unit at a preset check interval, and changes at least one setting among an initial accumulation amount to be used as a basis for starting to output the data accumulated in the accumulating unit, an upper accumulation limit amount to be used as a basis for discarding accumulated data, and a check interval, according to a discarded state of the data based on check results. Therefore, in the data output apparatus such as an IP telephony terminal apparatus, it is possible to prevent sound interruption and limit a lowering of communication quality.

Abstract: An interface requests instructions from a data store storing instructions of an application to be processed by a data processor, and receives and transmits the instructions to the data processor. The interface includes: an input that receives the instructions from the data store via at least one input bus; a buffer that stores received instructions; an output that outputs instructions to the data processing apparatus via the output bus; a control signal input that receives a control signal; and a buffer controller that controls the buffer to request an instruction subsequent to a previously received instruction within an instruction stream of the application from the data store in response to detection of no control signal on the control signal input and to detection of available buffer storage capacity.

Abstract: Methods and apparatus are disclosed for identifying a system. In various embodiments, values of identification codes are read from each of a plurality of electronic devices of the system. The values of the identification codes are used to generate a system identifier value.

Abstract: A method for improving timing behavior of a processing unit in a multithreading environment is disclosed, wherein the processing unit generates data frames for an output unit by combining data from a plurality of input units, and the processed data are buffered in an output buffer between the processing unit and the output unit. The method comprises sending from the output unit to the processing unit a value corresponding to the filling of the output buffer, calculating a timer value, setting a timer with the timer value, wherein the timer calls the processing unit thread after the specified time. The timer value depends on the value corresponding to the averaged filling of the output buffer. As a result, the average filling of the output buffer is lower compared to conventional thread management, and thus the system is more flexible and reacts quicker.

Abstract: A computer-implemented method includes steps of: coupling a portable device comprising a personal computing environment to a host computer system; booting the host computer system from the portable device; determining that the portable device does not have a driver for one or more hardware elements found in the host computer system; transmitting a request to a local zone provisioning server, for the one or more device drivers.

Abstract: An industrial controller may communicate with a number of input/output (I/O) modules using an optimized connection packet assembled by a scanner communicating directly with the I/O modules and forwarding the optimized connection packet to the industrial processor. The optimized connection packet is communicated over a connection as part of a connected messaging system used to ensure highly reliable network communication. The need for higher data rates for some I/O modules as part of the optimized connection packet may be accommodated through the opening of a second redundant connection that provides the high-data-rate data in an interleaving fashion with the optimized connection packet, without upsetting the optimized connection packet or changing the use of the data by the industrial control program.

Abstract: Mechanisms for configuring an integrated circuit to select one of multiple external device interfaces at a time to use during communication with external devices. The integrated circuit includes a control mechanism, a selection mechanism, and a plurality of external device interfaces. The plurality of device interfaces allow the integrated circuit to communicate with various external devices that support different communication protocols. The control mechanism is configured to designate the selection of one of the plurality of device interfaces for use in communicating with an external device. The control mechanism makes use of the selection mechanism to select the designated device interface to communicate with using the communication protocol supported by the selected interface. The communication may be receiving data from the interface or providing data to the interface. Non-selected interfaces are put in an inactive state.

Abstract: Some interface signals are selected from among signals of a plurality of different parallel interfaces, then being multiplexed onto a serial connection. A transmitter of a signal transmission system includes an interface-signal selector IFS, and a transfer programmer TP for issuing a control signal to instruct the selection from among the parallel interfaces. The transfer programmer TP implements the multiplexing of the selected interface signals in such a manner that the specification of the parallel interfaces is satisfied. Also, the transfer programmer TP changes, as occasion requires, the control signal to instruct which interfaces to select. This change allows the interface signals to be multiplexed onto the serial connection while dynamically changing the interface signals to be multiplexed.

Abstract: A system that includes a host including at least one per-connection data structure and at least one per-processor data structure, wherein the at least one per-connection data structure is associated with a connection, and an offload engine operatively connected to the host. The engine includes offload engine connection registers and functionality to update the at least one per-connection data structures in the host, wherein the offload engine is configured to send and receive network data on the connection, wherein the host and the offload engine communicate using the at least one per-processor data structure, and wherein the offload engine communicates a status of the connection to the host using the offload engine connection registers.

Abstract: One embodiment of the present invention sets forth a technique for mapping a small computer system interface (SCSI) architecture model-3 (SAM-3) task priority to an IEEE Standard 802.1q tag control information (TCI) field. Four bits that define a SAM-3 task priority are mapped to the three user priority bits within a standard 802.1q TCI field. By enabling the SAM-3 task priority of a given SCSI command to determine the user priority within a related IEEE 802.1q Ethernet frame, the Ethernet network is enabled to substantially honor the requested task priority for the SCSI command.

Abstract: An isolated data acquisition device including a plurality of data acquisition channels, an isolated system management unit coupled to the data acquisition channels, a host system management unit, a serial bus coupled to the host system management unit and the isolated system management unit, and isolation circuitry coupled to the serial bus. The isolation circuitry electrically isolates the host system management unit from the isolated system management unit and the data acquisition channels. During operation, the isolated system management unit and the host system management unit may each store data associated with one or more pending bus transactions. Each of the system management units may select at least one of the pending bus transactions according to a predetermined priority scheme, encode and serialize the data associated with the selected bus transaction, and transmit the serialized data across the isolation circuitry to the other system management unit via the serial bus.

Abstract: A method and system for memory address translation and pinning are provided. The method includes attaching a memory address space identifier to a direct memory access (DMA) request, the DMA request is sent by a consumer and using a virtual address in a given address space. The method further includes looking up for the memory address space identifier to find a translation of the virtual address in the given address space used in the DMA request to a physical page frame. Provided that the physical page frame is found, pinning the physical page frame al song as the DMA request is in progress to prevent an unmapping operation of said virtual address in said given address space, and completing the DMA request, wherein the steps of attaching, looking up and pinning are centrally controlled by a host gateway.

Abstract: In one embodiment, the present invention includes a method of determining a relative priority between a first agent and a second agent, and assigning the first agent to a first channel and the second agent to a second channel according to the relative priority. Depending on the currently programmed status of the channels, information stored in at least one of the channels may be dynamically migrated to another channel based on the assignments. Other embodiments are described and claimed.

Abstract: A data storage system having protocol controller for converting packets between PCIE format used by a storage processor and Rapid IO format used by a packet switching network. The controller includes a PCIE end point for transferring atomic operation (DSA) requests, a data pipe section having a plurality of data pipes for passing user data; and a message engine section for passing messages among the plurality of storage processors. An acceleration path controller bypasses a DSA buffer in the absence of congestion on the network. Packets fed to the PCIE end point include an address portion having code indicating an atomic operation. An encoder converts the code from a PCIE format into the same atomic operation in SRIO format. Each one of a plurality of CPUs is adapted to perform a second DSA request during execution of a first DSA request.

Abstract: A data processing device is provided using pipeline architecture to reduce a time loss due to a branch without causing an increase in circuit scale. The data processing device uses pipeline control. The data processing device includes an instruction queue in which a plurality of instruction codes can be fetched, a fetch address operation circuit which calculates a fetch address, a fetch circuit which fetches an instruction code based on the fetch address, and a branch information setting circuit which decodes a branch setting instruction, stores a branch address in a branch address storage register, and stores a branch target address in a branch target address storage register. The fetch address operation circuit compares either a previous fetch address or an expected next fetch address with a value stored in the branch address storage register, and determines a next fetch address to be output, based on the comparison result.

Abstract: A universal serial bus (USB) dongle device includes a wireless telephony transceiver that receives an inbound RF signal and that generates inbound data based on the inbound RF signal and receives outbound data and that generates an outbound RF signal in response thereto. A USB plug is connectable to a host device. A USB controller circuit formats the inbound data in the USB format for communication to the host device and to recover the outbound data from outbound data received in the USB format from the host device. A millimeter wave interface includes a first millimeter wave transceiver coupled to the wireless transceiver and a second millimeter wave transceiver coupled to the USB controller circuit that wirelessly communicates the inbound data and the outbound data between the wireless telephony receiver and the USB controller circuit.

Abstract: A local electrical signal and a remote electrical signal are received for switching. When destinations of the local and remote electrical signals are the same local signal input device, only one of them is allowed to be transmitted to the destined local signal input device. When destinations of the local and remote electrical signals are at least one remote signal input device, only one of them is allowed to be transmitted to the destined remote signal input device.