Abstract: An emulator schedules emulation threads for DMA emulation and other emulation functions in a time-multiplexed manner. Emulation threads are selected for execution according to a load balancing scheme. Non-DMA emulation threads are executed until their execution time period expires or they stall. DMA emulation thread execution is allowed to execute indefinitely until the DMA emulation thread stalls. The DMA emulation thread prefetches additional adjacent data in response to target computer system DMA requests. Upon receiving a target computer system DMA request, the DMA emulation thread first checks to the prefetched data to see if this data matches the request. If so, the request is fulfilled using the prefetched data. If the prefetched data does not match the target computer system DMA request, the DMA emulation thread fetches and stores the requested data and additional adjacent data for potential future use.

Abstract: An operation monitor system externally outputs a sufficient amount of condition information that indicates an internal operation condition, without using a dedicated terminal, that is to say, without a significant increase in cost. An output control unit of a semiconductor apparatus specifies an IF unit that is not currently performing input/output with respect to an IO unit, selects a selector connected to the specified IF unit, and outputs thereto a select signal indicating that the selected selector is to be used in the output of an internal operation output signal (internal monitoring data), which is the operation condition. The selector that has received the select signal selects the internal condition output signal, and outputs the selected internal condition output signal to an information collection apparatus via the IO unit.

Abstract: A plurality of memory devices of mixed type (e.g., DRAMs, SRAMs, MRAMs, and NAND-, NOR- and AND-type Flash memories) is serially interconnected. Each device has device type information on its device type. A specific device type (DT) and a device identifier (ID) contained in a serial input (SI) as a packet are fed to one device of the serial interconnection. The device determines whether the fed DT matches the DT of the device. In a case of match, a calculator included in the device performs calculation to generate an ID accompanying the fed DT for another device and the fed ID is latched in a register of the device. In a case of no match, the ID generation is skipped and no ID is generated for another device. The DT is combined with the generated or the received ID depending on the device type match determination. The combined DT and ID is as a packet transferred to a next device. Such a device type match determination and ID generation or skip are performed in all devices of the serial interconnection.

Abstract: Provided are a system and article of manufacture for executing initialization code to configure connected devices. A plurality of segments are provided to configure at least one connected device, wherein each segment includes configuration code to configure the at least on connected device. The segments are executed according to a segment order by executing the configuration code in each segment to perform configuration operations with respect to the at least one connected device. Completion of the segment is indicated in a memory in response to completing execution of the configuration operations for the segment.

Abstract: An apparatus and method are provided that enable I/O devices to be shared and/or partitioned among a plurality of operating system domains within the load-store fabric of each of the operating system domains without requiring modification to the operating system or driver software of the operating system domains. The apparatus includes sharing logic and a first shared input/output (I/O) endpoint. The sharing logic is coupled to a plurality of operating system domains through a load-store fabric. The sharing logic routes transactions between the plurality of operating system domains. The first shared input/output (I/O) endpoint is coupled to the sharing logic. The first shared I/O endpoint requests/completes the transactions for the each of said plurality of operating system domains according to a variant of a protocol that encapsulates an OS domain header within a transaction layer packet.

Abstract: A buffer control method for controlling packets to be stored in a buffer having a data region and a command queue region. First, the number of the packets that can be stored in the data buffer is determined. Then, a count value representing the remained capacity of the data region is updated. Finally, the count value and a value of maximum data length are compared to determine whether to increase the number of the packets that can be stored in the buffer.

Abstract: Embodiments are generally direct to a method and apparatus to generate a data descriptor. In one embodiment, a data descriptor is generated for a block of data to be forwarded from a node to another node on a communication link. The data descriptor includes an indication to build a data packet containing at least a portion of the block of data in an accelerated or a non-accelerated manner.

Abstract: In a USB device comprising a plurality of functional modules that includes a control circuit for switching a functional module to be activated from among the functional modules included in the USB device according to a potential level of a power applied from a host connected to the USB device. The control circuit includes: a voltage detector for discriminating a voltage value of power; a switch for controlling powers to be applied to the respective functional modules; and memories for storing descriptors relating to the USB device. The control circuit makes power applied to a functional module to be activated by the switch into ON state according to a discrimination result of the voltage value of the power by the voltage detector, thereby transferring the descriptors stored in the memories to a host.

Abstract: A method of dynamic data transfer width adjustment is provided. The method includes firstly detects a data size of a transfer data. A data transfer width mode is detected according to a data address of transferring data. The data transfer width mode includes at least one of a word mode, a half-word mode, and a byte mode. According to the data address, the data transfer width mode, and the data size, the data is transferred.

Abstract: A device interface circuit unit transfers a command and data in packet format between the unit and the host. A transport layer is provided with a receive FIFO, a command detection circuit and a send FIFO, and an application layer is provided with a receive task file register and a send task control file register. An available time is generated for each break point of a packet during data transfer in order to receive another command packet from the host. When the command packet is received from the host in the available time during data transfer, the data transfer is suspended and the received command is decoded to execute a process for continuing or canceling the data transfer, after which the data transfer is resumed.

Abstract: In one embodiment, payload of multiple threads between intellectual property (IP) cores of an integrated circuit are transferred, by buffering the payload using a number of order queues. Each of the queues is guaranteed access to a minimum number of buffer entries that make up the queue. Each queue is assigned to a respective thread. A number of buffer entries that make up any queue is increased, above the minimum, by borrowing from a shared pool of unused buffer entries on a first-come, first-served basis. In another embodiment, an interconnect implements a content addressable memory (CAM) structure that is shared storage for a number of logical, multi-thread ordered queues that buffer requests and/or responses that are being routed between data processing elements coupled to the interconnect. Other embodiments are also described and claimed.

Abstract: A command generating and monitoring system includes a command processor configured to determine a command data set from a command input. A monitoring processor is coupled to the command processor and is configured to generate an authentication key by comparing the command data set received from the command processor to a comparison command data set generated by the monitoring processor. A data bus is coupled to the command processor and the monitoring processor. The data bus is configured to receive the command data set and the authentication key for retrieval by a consuming device.

Abstract: Methods and apparatus for host-side Serial ATA Native Command Queuing (NCQ) tag management are disclosed. In one aspect, an exemplary apparatus may include a memory and an NCQ tag selection circuit in communication with the memory. The memory may store information for each of a plurality of different NCQ tag values. The information for each NCQ tag value may indicate whether or not a command having the NCQ tag value has been issued. The NCQ tag selection circuit may examine the information in the memory, and may select an NCQ tag value having information that indicates that a command having the NCQ tag value has not been issued. Systems and architectures including such apparatus are also disclosed.

Abstract: A memory controller includes a control circuit configured to provide a control signal, an output interface unit, and a command storage unit coupled to the control circuit and the output interface. The command storage unit is configured to store a plurality of commands, receive the control signal, and provide, in response to the control signal, a selected command of the plurality of commands to the output interface unit.

Abstract: A memory controller provides page copy logic that assures data coherency when a DMA operation to a page occurs during the copying of the page by the memory controller. The page copy logic compares the page index of the DMA operation to a copy address pointer that indicates the location currently being copied. If the page index of the DMA operation is less than the copy address pointer, the portion of the page that would be written to by the DMA operation has already been copied, so the DMA operation is performed to the physical address of the new page. If the page index of the DMA operation is greater than the copy address pointer, the portion of the page that would be written to by the DMA operation has not yet been copied, so the DMA operation is performed to the physical address of the old page.

Abstract: Methods, apparatuses and systems directed to virtualized access to input/output (I/O) subsystems. In one implementation, the present invention allows multiple stand-alone application servers or virtual servers to share one or more I/O subsystems, such as host-bus adapters and network interface cards. In one implementation, I/O access is managed by one or more virtual I/O servers. A virtual I/O server includes a multiplexer, and associated modules, that connect application servers over an I/O switch fabric with one or more HBA and/or NIC drivers. Implementations of the present invention can be configured to consolidate I/O access, allowing multiple servers to share one or more HBAs and NICs; dynamic control over network and storage I/O bandwidth; and provisioning of network and storage I/O access across multiple application servers.

Abstract: Methods, apparatus, and products are disclosed for DMA transfer completion notification that include: inserting, by an origin DMA engine on an origin compute node in an injection FIFO buffer, a data descriptor for an application message to be transferred to a target compute node on behalf of an application on the origin compute node; inserting, by the origin DMA engine, a completion notification descriptor in the injection FIFO buffer after the data descriptor for the message, the completion notification descriptor specifying an address of a completion notification field in application storage for the application; transferring, by the origin DMA engine to the target compute node, the message in dependence upon the data descriptor; and notifying, by the origin DMA engine, the application that the transfer of the message is complete, including performing a local direct put operation to store predesignated notification data at the address of the completion notification field.

Abstract: First and second networks, for example Controller Area Networks (CANs), of different physical layers are interfaced by applying signals of the busses of the two networks to respective transceivers. A dominant state of one of the busses is sensed and data is transferred between the two transceivers in a direction from the dominant bus. The two busses are interfaced by a logic circuit interposed between the transceivers. A control circuit is coupled to the first and second logic units for mutually exclusively activating and deactivating the first and second logic units to control the direction of data transfer between the busses.

Abstract: A direct memory access controlling method includes checking a length value of remaining data corresponding to data remaining after transmission of the data stored in the source memory to the destination memory, and a currently set burst length value, comparing the length value of the remaining data with the currently set burst length value based on a result of the checking, and selectively changing the currently set burst length value based on a result of the comparing, and transmitting data to the destination memory.

Abstract: One embodiment provides a system which uses a temporal ordering policy for allocation of limited processor resources. The system starts by executing instructions for a program during a normal-execution mode. Upon encountering a condition which causes the processor to enter a speculative-execution mode, the processor performs a checkpoint and commences execution of instructions in the speculative-execution mode. Upon encountering an instruction which requires the allocation of an instance of a limited processor resource during the execution of instructions in the speculative-execution mode, the processor checks a speculative-use indicator associated with each instance of the limited processor resource. Upon finding the speculative-use indicators asserted for all instances of the limited processor resource which are available to be allocated for the instruction, the processor aborts the instruction.