Patents Examined by Farley J Abad
  • Patent number: 7581045
    Abstract: Provided are a method, system, and article of manufacture for mapping programming interfaces. A synchronous request for reading data is received. An asynchronous request to fill selected buffers of a plurality of buffers is sent. The synchronous request is responded to with the data from at least one buffer of the plurality of buffers.
    Type: Grant
    Filed: June 14, 2005
    Date of Patent: August 25, 2009
    Assignee: Intel Corporation
    Inventors: John A. Wiegert, Stephen D. Goglin
  • Patent number: 7571264
    Abstract: Provided is a computer system which includes computers and a storage system coupled to the computers. The storage system includes a first load measuring module that measures a first access load for each channel adaptor. At least one of the computers includes a path management module that manages paths through which the computers access logical units. The path management module includes a second load measuring module that measures a second access load imposed by access from the computer to the logical unit, and an active path setting module that selects one of the channel adaptors based on the first access and the second access load measured by the first and second load measuring modules, and setting an active path passing through the channel adaptor. Thus, a load on an entire system is balanced, thereby improving performance while a cache hit rate of a storage system is maintained.
    Type: Grant
    Filed: July 26, 2005
    Date of Patent: August 4, 2009
    Assignees: Hitachi, Ltd., Hitachi Software Engineering Co., Ltd.
    Inventors: Hirofumi Sahara, Hiroshi Morishima, Makoto Aoki, Osamu Kohama, Satoshi Kadoiri, Isao Nagase
  • Patent number: 7548999
    Abstract: In one embodiment, an input/output (I/O) node comprises an I/O memory management unit (IOMMU) configured to translate memory requests. The I/O node is configured to couple to an interconnect and to operate as a tunnel on the interconnect, and wherein the IOMMU is configured translate memory requests passing through the tunnel in the upstream direction. In another embodiment, a system comprises another I/O node configured to bridge another interconnect to the interconnect, wherein the I/O node is the tunnel for the other I/O node.
    Type: Grant
    Filed: January 16, 2007
    Date of Patent: June 16, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Michael Haertel, Mark D. Hummel, Geoffrey S. Strongin, Andrew W. Lueck, Mitchell Alsup
  • Patent number: 7548964
    Abstract: Performance counters are provided for virtualized network interfaces of communications networks, while minimizing the use of hardware resources. A virtualized network interface includes physical resources, as well as logical resources. Dedicated performance counters are provided for the physical resources of the virtualized network interface, as well as for logical partitions coupled to that interface, while non-dedicated performance counters are provided for the logical resources. This enables the provision of performance counters for virtualized network interfaces, while minimizing hardware resources consumed by those interfaces.
    Type: Grant
    Filed: October 11, 2005
    Date of Patent: June 16, 2009
    Assignee: International Business Machines Corporation
    Inventors: Richard L. Arndt, Bruce L. Beukema, David Craddock, Ronald E. Fuhs, Thomas A. Gregg, Donald W. Schmidt, Bruce M. Walk
  • Patent number: 7546397
    Abstract: Methods and systems for allowing multiple devices to share the same serial lines (e.g., SDIO, SEN and SCLK) are provided. Such devices can be located, e.g., on an optical pick-up unit. Each device includes a serial interface, a device enable number (DEN) that differs from the DEN of each other device, and a plurality of registers, with at least one register being designated a device select register (DSR). The DSRs of the plurality of devices share a common address. The plurality of serial interfaces are collectively enabled and collectively disabled (e.g., via the SEN line). However, only one of the plurality of serial interfaces can be selected at one time, with the remaining of the plurality of serial interfaces being deselected. The serial interface of a device is selected when the DEN of the device is the same as the content of the DSR of the device, and deselected when the DEN of the device is not the same as the content of the DSR of the device.
    Type: Grant
    Filed: January 19, 2007
    Date of Patent: June 9, 2009
    Assignee: Intersil Americas Inc.
    Inventors: Theodore D. Rees, D. Stuart Smith, Dong Zheng
  • Patent number: 7533198
    Abstract: A memory controller provides page copy logic that assures data coherency when a DMA operation to a page occurs during the copying of the page by the memory controller. The page copy logic compares the page index of the DMA operation to a copy address pointer that indicates the location currently being copied. If the page index of the DMA operation is less than the copy address pointer, the portion of the page that would be written to by the DMA operation has already been copied, so the DMA operation is performed to the physical address of the new page. If the page index of the DMA operation is greater than the copy address pointer, the portion of the page that would be written to by the DMA operation has not yet been copied, so the DMA operation is performed to the physical address of the old page.
    Type: Grant
    Filed: October 7, 2005
    Date of Patent: May 12, 2009
    Assignee: International Business Machines Corporation
    Inventors: Gerald Keith Bartley, John Michael Borkenhagen, William Paul Hovis, Daniel Paul Kolz
  • Patent number: 7467241
    Abstract: A control system for a plurality of storage systems has at least one path that is selected from a plurality of paths where one of three or more storage systems is a start point storage system and another one thereof is an end point storage system. According to the selected path, the external connection processing for writing data to an external volume which corresponds to a virtual volume, and/or the remote copy processing for writing data to be written in a copy source volume to a copy destination volume, is/are executed at least once. By this, the data received by the start point storage system is written to the logical volume in the end point storage system.
    Type: Grant
    Filed: October 13, 2005
    Date of Patent: December 16, 2008
    Assignee: Hitachi, Ltd.
    Inventor: Yusuke Masuyama