Abstract: A photoelectric conversion element according to an embodiment of the present disclosure includes: a first electrode and a second electrode facing each other; and a photoelectric conversion layer provided between the first electrode and the second electrode, and including a first organic semiconductor material, a second organic semiconductor material, and a third organic semiconductor material that have mother skeletons different from one another. The first organic semiconductor material is one of fullerenes and fullerene derivatives. The second organic semiconductor material in a form of a single-layer film has a higher linear absorption coefficient of a maximal light absorption wavelength in a visible light region than a single-layer film of the first organic semiconductor material and a single-layer film of the third organic semiconductor material. The third organic semiconductor material has a value equal to or higher than a HOMO level of the second organic semiconductor material.

Abstract: An imaging element has at least a photoelectric conversion section, a first transistor TR1, and a second transistor TR2, the photoelectric conversion section includes a photoelectric conversion layer 13, a first electrode 11, and a second electrode 12, the imaging element further has a first photoelectric conversion layer extension section 13A, a third electrode 51, and a fourth electrode 51C, the first transistor TR1 includes the second electrode 12 that functions as one source/drain section, the third electrode that functions as a gate section 51, and the first photoelectric conversion layer extension section 13A that functions as the other source/drain section, and the first transistor TR1 (TRrst) is provided adjacent to the photoelectric conversion section.

Abstract: A BSI image sensor includes a substrate including a front side and a back side opposite to the front side, a pixel sensor disposed in the substrate, and a color filter disposed over the pixel sensor. The pixel sensor includes a plurality of first micro structures disposed over the back side of the substrate. The color filter includes a plurality of second micro structures disposed over the back side of the substrate. The first micro structures are arranged symmetrically to a first axial, and the second micro structures are arranged symmetrically to a second axial.

Abstract: A display device includes a first electrode, a pixel define layer disposed on the first electrode, the pixel define layer including an opening, an organic emission layer disposed on the pixel define layer, the organic emission layer in electrical communication with the first electrode through the opening, a second electrode disposed on the organic emission layer, a light recycle layer disposed on the second electrode, and a color filter layer disposed on the light recycle layer, the color filter layer including a quantum dot, wherein a width of the organic emission layer is longer than a width of the color filter layer.

Abstract: A method for making a multilayered device on an engineered substrate having a substrate coefficient of thermal expansion includes growing a buffer layer on the engineered substrate, and growing a first epitaxial layer on the buffer layer. The first epitaxial layer is characterized by an epitaxial coefficient of thermal expansion substantially equal to the substrate coefficient of thermal expansion.

Abstract: A display panel, a manufacturing method thereof and a display device are provided. The display panel includes a display area and a hole forming area, where the display area surrounds the hole forming area, and an organic material layer is provided in the hole forming area so that a height difference between the hole forming area and the display area is less than a threshold value of 4 um.

Abstract: Wells formed in a semiconductor device can be discharged faster in a transition from a stand-by state to an active state. The semiconductor device includes an n-type well applied, in an active state, with a power supply voltage and, in a stand-by state, with a voltage higher than the power supply voltage, a p-type well applied, in the active state, with a ground voltage and, in the stand-by state, with a voltage lower than the ground voltage, and a path which, in a transition from the stand-by state to the active state, electrically couples the n-type well and the p-type well.

Abstract: The present disclosure provides a semiconductor device having a buried wordline. The semiconductor device includes a substrate having a surface and a first dielectric layer extending from the surface of the substrate into the substrate. The semiconductor device also includes a second dielectric layer disposed on the first dielectric layer and extending from the surface of the substrate into the substrate and a first conductive layer disposed in the substrate and separated from the substrate by the first dielectric layer and the second dielectric layer.

Abstract: An embodiment of the disclosure is a structure comprising an interposer. The interposer has a test structure extending along a periphery of the interposer, and at least a portion of the test structure is in a first redistribution element. The first redistribution element is on a first surface of a substrate of the interposer. The test structure is intermediate and electrically coupled to at least two probe pads.

Abstract: An electronic device includes a substrate semiconductor wafer with semiconductor portions separated from one another by through-passages. Electronic circuits and a dielectric layer with a network of electrical connections are formed at a front face of the substrate semiconductor wafer. Electrically conductive fillings are contained within the through-passages and are connected to the network of electrical connections. Interior dielectric layers for anti-diffusion protection are provided in the through-passages between the electrically conductive fillings and the semiconductor portions. Back side dielectric layers are joined to the interior dielectric layers.

Abstract: A semiconductor package includes a lower substrate including a lower passivation layer, a lower pad, element pads and a supporting pad that are disposed on a lower surface of the lower substrate. The lower passivation layer partially covers the lower pad, the element pads and the supporting pad. A semiconductor chip is disposed on an upper surface of the lower substrate. An upper substrate is disposed on the semiconductor chip and is connected to the lower substrate. An encapsulator is disposed between the lower substrate and the upper substrate. An element is disposed on the lower surface of the lower substrate. The element is bonded to the element pads. A lower supporting member is disposed on the lower surface of the lower substrate. A supporting bonding member bonds the lower supporting member to the supporting pad.

Abstract: A layout of a semiconductor device stored on a non-transitory computer-readable medium includes a first transistor in an active device region, the first transistor comprising a first channel region a first source region and a first drain region. The layout further includes a second transistor in a guard ring region, the second transistor comprising a second channel region a second source region and a second drain region. The second channel region includes a semiconductor material having a higher thermal conductivity than a semiconductor material of the first channel region.

Abstract: An electronic device includes a dielectric layer including crystal grains having aligned crystal orientations the dielectric layer may be between a substrate and a gate electrode. The dielectric layer may be between isolated first and second electrodes. A method of manufacturing an electronic device may include preparing a substrate having a channel layer, forming the dielectric layer on the channel layer, and forming a gate electrode on the dielectric layer.

Abstract: Provided is an electronic substrate that achieves a reduction in the size of a substrate and enables a void risk in an underfill to be reduced, and an electronic apparatus. The electronic substrate includes an electronic chip that is placed above a substrate, an electrode that exists between the substrate and the electronic chip and electrically connects the substrate and the electronic chip, an underfill with which a space between the substrate and the electronic chip is filled so that the electrode is sealed and protected, a protection target to be protected from inflow of the underfill, the protection target being formed on the substrate, and an underfill inflow prevention unit that is formed in the substrate so as to surround an entirety or a portion of the protection target.

Abstract: A semiconductor structure includes a substrate, a channel layer, a barrier layer, a source structure, a drain structure, a doped compound semiconductor layer, a dielectric layer, and a gate structure. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The source structure and the drain structure are disposed on opposite sides of the barrier layer. The doped compound semiconductor layer is disposed on the barrier layer. The doped compound semiconductor layer has a first side adjacent to the source structure and a second side adjacent to the drain structure. The doped compound semiconductor layer has at least one opening exposing at least a portion of the barrier layer. The dielectric layer is disposed on the doped compound semiconductor layer and the barrier layer. The gate structure is disposed on the doped compound semiconductor layer.

Abstract: A structure includes an SRAM cell includes a first and a second pull-up MOS device, and a first and a second pull-down MOS device forming cross-latched inverters with the first pull-up MOS device and the second pull-up MOS device. A first metal layer is over the gate electrodes of the MOS devices in the SRAM cell. The structure further includes a first metal layer, and a CVss landing pad, wherein the CVss landing pad has a portion in the SRAM cell. The CVss landing pas is in a second metal layer over the first metal layer. A word-line is in the second metal layer. A CVss line is in a third metal layer over the second metal layer. The CVss line is electrically coupled to the CVss landing pad.

Abstract: A conductive film includes an elongated release film and a plurality of conductive adhesive film pieces provided on the release film. Then, the plurality of adhesive film pieces are arranged in a longitudinal direction X of the release film. For this reason, the adhesive film piece can be set to an arbitrary shape. Accordingly, it is possible to attach the adhesive film piece to adhesive surfaces having various shapes and to efficiently use the adhesive film piece.

Abstract: An organic light emitting diode display device includes a substrate including at least one subpixel having a non-emitting area and an emitting area; a thin film transistor in the non-emitting area on the substrate; an overcoating layer on the thin film transistor and having a plurality of microlenses at a top surface of the overcoating layer; and a light emitting diode in the emitting area on the overcoating layer and connected to the thin film transistor, wherein a surface of the plurality of microlenses in a sampling area of the emitting area is divided into a plurality of convex portions and a plurality of concave portions with respect to a central surface, and a total volume of the plurality of convex portions with respect to the central surface is equal to a total volume of the plurality of concave portions with respect to the central surface.

Abstract: A high resistivity wafer with a heat dissipation structure includes a high resistivity wafer and a metal structure. The high resistivity wafer includes a heat dissipation region and a device support region. The high resistivity wafer consists of an insulating material. The metal structure is only embedded within the heat dissipation region of the high resistivity wafer. The metal structure surrounds the device support region.

Abstract: Disclosed is a light emitting display device which may block lateral leakage current. The light emitting display device includes electrode patterns arranged under a bank between adjacent subpixels so as to form a vertical channel, the bank covered by the electrode patterns functions as a gate insulating film and thus dielectric polarization occurs therein, and charges move from a common layer having high hole mobility to a common layer having low hole mobility, thereby being capable of preventing lateral leakage current.