Abstract: A method of forming memory circuitry comprises using a digitline mask to form both: (a) conductive digitlines in a memory array area, and (b) lower portions of conductive vias in a peripheral circuitry area laterally of the memory array area. The lower portions of the vias electrically couple with circuitry below the vias and the digitlines. Pairs of conductive wordlines are formed above the digitlines in the memory array area. The pairs of wordlines extend from the memory array area into the peripheral circuitry area. Individual of the pairs are directly above individual of the lower portions of individual of the vias. Individual upper portions of the individual vias are formed. The individual upper portions both: (c) directly electrically couple to one of the individual lower portions of the individual vias, and (d) directly electrically couple together the wordlines of the individual pair of wordlines that are directly above the respective one individual lower portion of the respective individual via.

Abstract: A method of forming a power semiconductor device includes providing an epi layer over a substrate; forming a well at an upper portion of the epi layer; forming a pillar below the well and spaced apart from the well to define a Schottky contact region; etching a trench into the epi layer, the trench having a sidewall and a base, a portion of the sidewall of the trench corresponding to the Schottky contact region; forming a metal contact layer over the sidewall and the base of the trench, the metal contact layer forming a Schottky interface with the epi layer at the Schottky contact region; and forming a gate electrode and first and second electrodes.

Abstract: Device structures are provided that include one or more plasmonic OLEDs and zero or more non-plasmonic OLEDs. Each plasmonic OLED includes an enhancement layer that includes a plasmonic material which exhibits surface plasmon resonance that non-radiatively couples to an organic emissive material and transfers excited state energy from the emissive material to a non-radiative mode of surface plasmon polaritons in the plasmonic OLED.

Abstract: The present disclosure relates to a Gallium-Nitride (GaN) based module, which includes a module substrate, a thinned switch die residing over the module substrate, a first mold compound, and a second mold compound. The thinned switch die includes an electrode region, a number of switch interconnects extending from a bottom surface of the electrode region to the module substrate, an aluminium gallium nitride (AlGaN) barrier layer over a top surface of the electrode region, a GaN buffer layer over the AlGaN barrier layer, and a lateral two-dimensional electron gas (2DEG) layer realized at a heterojunction of the AlGaN barrier layer and the GaN buffer layer. The first mold compound resides over the module substrate, surrounds the thinned switch die, and extends above a top surface of the thinned switch die to form an opening over the top surface of the thinned switch die. The second mold compound fills the opening.

Abstract: An anchored cut-metal gate (CMG) plug, a semiconductor device including the anchored CMG plug and methods of forming the semiconductor device are disclosed herein. The method includes performing a series of etching processes to form a trench through a metal gate electrode, through an isolation region, and into a semiconductor substrate. The trench cuts-through and separates the metal gate electrode into a first metal gate and a second metal gate and forms a recess in the semiconductor substrate. Once the trench has been formed, a dielectric plug material is deposited into the trench to form a CMG plug that is anchored within the recess of the semiconductor substrate and separates the first and second metal gates. As such, the anchored CMG plug provides high levels of resistance to reduce leakage current within the semiconductor device during operation and allowing for improved V-trigger performance of the semiconductor device.

Abstract: A functional layer forming ink used in forming a functional layer of the self-luminous element by a printing method, the ink including functional material dissolved or dispersed in a mixed solvent including solvents having different boiling points. When one or more solvents are selected from the solvents of the mixed solvent in descending order of boiling point until a mass ratio of the selection to the mixed solvent is a defined ratio or more, the one or more solvents in the selection are included in a solvent group of solvents that have a contact angle of 5° or less with respect to a defined resin material.

Abstract: A high resistivity wafer with a heat dissipation structure includes a high resistivity wafer and a metal structure. The high resistivity wafer includes a heat dissipation region and a device support region. The high resistivity wafer consists of an insulating material. The metal structure is only embedded within the heat dissipation region of the high resistivity wafer. The metal structure surrounds the device support region.

Abstract: In an embodiment, a method of forming a semiconductor device includes forming a dummy gate stack over a substrate; forming a first spacer layer over the dummy gate stack; oxidizing a surface of the first spacer layer to form a sacrificial liner; forming one or more second spacer layers over the sacrificial liner; forming a third spacer layer over the one or more second spacer layers; forming an inter-layer dielectric (ILD) layer over the third spacer layer; etching at least a portion of the one or more second spacer layers to form an air gap, the air gap being interposed between the third spacer layer and the first spacer layer; and forming a refill layer to fill an upper portion of the air gap.

Abstract: A display apparatus includes a substrate on which a central area and a peripheral area adjacent to the central area are arranged. The central area includes a display area. The display apparatus further includes: at least one insulation pattern that is formed in the peripheral area; a groove from which a material for forming the insulation pattern is removed and that is formed adjacent to the insulation pattern; and at least one insulating layer that is interposed between the insulation pattern and the substrate. The groove is located in the at least one insulating layer.

Abstract: A system and method for adding a source contact, a drain contact, and an apparent gate contact to a FinFET having a fin including a source region, a drain region, and a gate disposed over the fin forming one or more transistor junctions with the fin. The method comprises producing a source contact opening extending downward to a first region electrically coupled to the source region, a drain contact opening extending downward to a second region electrically coupled to the drain region, and a gate contact opening extending downward to a third region electrically isolated from the gate, and filling the source contact opening, the drain contact opening, and the gate contact opening with a conductive metal.

Abstract: A method of manufacturing a display device includes preparing a substrate, wherein the substrate includes a pixel area and a transmission area, forming insulating layers in the pixel area and in the transmission area, forming a pixel electrode on the insulating layers in the pixel area and forming a pixel-defining layer on the pixel electrode, wherein the pixel-defining layer exposes at least part of the pixel electrode, forming a metal layer on the pixel-defining layer in the pixel area, the at least part of the pixel electrode exposed by the pixel-defining layer in the pixel area, and the insulating layers in the transmission area, removing the metal layer on the insulating layers in the transmission area, and removing the insulating layers in the transmission area.

Abstract: A semiconductor package includes a multilayer package substrate including a first layer including a first dielectric and first metal layer including a first metal trace and a second layer including a second dielectric layer. An integrated circuit (IC) die includes bond pads, with a bottom side of the IC die attached to the first metal trace. Metal pillars are through the second dielectric layer connecting to the first metal trace. A third layer on the second layer includes a third dielectric layer on the second layer extending to a bottom side of the semiconductor package, and a second metal layer including second metal traces including inner second metal traces connected to the bond pads and outer second metal traces over the metal pillars, and filled vias providing externally accessible contact pads that connect the second metal traces to a bottom side of the semiconductor package.

Abstract: The present disclosure relates to a Gallium-Nitride (GaN) based module, which includes a module substrate, a thinned switch die residing over the module substrate, a first mold compound, and a second mold compound. The thinned switch die includes an electrode region, a number of switch interconnects extending from a bottom surface of the electrode region to the module substrate, an aluminium gallium nitride (AlGaN) barrier layer over a top surface of the electrode region, a GaN buffer layer over the AlGaN barrier layer, and a lateral two-dimensional electron gas (2DEG) layer realized at a heterojunction of the AlGaN barrier layer and the GaN buffer layer. The first mold compound resides over the module substrate, surrounds the thinned switch die, and extends above a top surface of the thinned switch die to form an opening over the top surface of the thinned switch die. The second mold compound fills the opening.

Abstract: The present disclosure provides a display substrate and a manufacturing method thereof, and a display device. The display substrate includes a base substrate and a driving circuit layer located on the base substrate, each of the plurality of pixel units comprises a light emitting element, wherein a display surface of the display substrate comprises a central display region and a plurality of peripheral display regions located around the central display region, a light emitting element in the central display region is an organic light emitting diode, and a light emitting element in at least one of the plurality of peripheral display regions is a micro light emitting diode.

Abstract: The present disclosure discloses an organic electroluminescence display panel, a method for manufacturing the display panel, and a display apparatus. The organic electroluminescence display panel includes: a substrate including a first region and a second region adjacent to each other; a buffer layer located on the substrate; a first active layer located on the buffer layer in the first region; a first gate located on the first active layer and insulated from the first active layer; a second active layer located on the buffer layer in the second region; a metal electrode located on the first gate and insulated from the first gate; and a second gate located on the second active layer and insulated from the second active layer.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a hard mask on a substrate; forming a first mandrel and a second mandrel on the hard mask; forming a first spacer and a second spacer around the first mandrel and a third spacer and a fourth spacer around the second mandrel; removing the second mandrel; forming a patterned mask on the first mandrel, the first spacer, the second spacer, the third spacer, and the fourth spacer; and using the patterned mask to remove the third spacer and the hard mask.

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region, a first electrode, and a first insulating member. The first semiconductor region includes Alz1Ga1-z1N (0?z1<1). The first semiconductor region includes a first partial region. The first insulating member includes a first insulating portion between the first partial region and the first electrode. The first insulating portion includes a first insulating region and a second insulating region. The second insulating region is provided between the first insulating region and the first electrode. The first insulating region includes Al1-x1Six1O (x1<0.5). The second insulating region includes Al1-x2Six2O (0.5<x2).

Abstract: An electroluminescent display device includes a substrate on which a display area displaying an image and a non-display area surrounding the display area are defined; a plurality of sub-pixels disposed in the display area on the substrate and arranged along a first direction and a second direction; a plurality of dummy sub-pixels disposed in the non-display area on the substrate; and a bank disposed in the display area and the non-display area on the substrate, wherein the bank includes a first portion corresponding to the plurality of sub-pixels and a second portion corresponding to the plurality of dummy sub-pixels, and wherein a side surface of the first portion has a reverse slope and at least a part of a side surface of the second portion has a normal slope.

Abstract: A package includes a die and a redistribution layer. A top surface of the die has a first area and a second area connected with the first area. The redistribution layer structure includes a first insulation layer, a redistribution layer, and a second insulation layer. The first insulation layer is overlapping with the second area. The redistribution layer is disposed above the die. The second insulation layer is disposed above the redistribution layer and overlapping with the second area and the first area. The second insulation layer covers a top surface of the first insulation layer and is in contact with a side surface of the first insulation layer and the top surface of the die.

Abstract: An electroluminescent display device comprises a substrate, a first electrode on the substrate, a connection pattern on the substrate and spaced apart from the first electrode, a bank covering edges of the first electrode and the connection pattern, a light-emitting layer on the first electrode, and a second electrode on the light-emitting layer, the bank and the connection pattern, wherein the connection pattern includes at least one protrusion part and a flat part, and wherein each of the first electrode and the connection pattern includes a first layer and a second layer, the second layer is disposed between the substrate and the first layer, and the second layer of the connection pattern has the at least one protrusion part.