Abstract: In some examples, a system may include a plurality of memory blocks, a first data bus coupled to the plurality of memory blocks in a memory device, a second data bus coupled to the plurality of memory blocks, a controller configured to perform memory read and write operations on the plurality of memory blocks via the first data bus, and a non-volatile storage (NVS) data transfer circuit configured to transfer data in a first memory block of the plurality of memory blocks to a NVS device via the second data bus. The first memory block may be a cold data block least accessed among the plurality of memory blocks. The cold data transfer may be performed via the second data bus when a different memory block is being accessed via the first data bus concurrently. The second data bus may be a fuse bus in the memory device.

Abstract: A heterogeneous processor system includes a first processor implementing an instruction set architecture (ISA) including a set of ISA features and configured to support a first subset of the set of ISA features. The heterogeneous processor system also includes a second processor implementing the ISA including the set of ISA features and configured to support a second subset of the set of ISA features, wherein the first subset and the second subset of the set of ISA features are different from each other. When the first subset includes an entirety of the set of ISA features, the lower-feature second processor is configured to execute an instruction thread by consuming less power and with lower performance than the first processor.

Abstract: The present disclosure generally relates to methods and systems for allocating free blocks as decommissioned blocks to replace bad blocks. In certain embodiments, when there are insufficient free blocks in a free block list to replace a bad or defective block for a CE, an FTL scans blocks stored in an unallocated block repository. If there are unallocated blocks available for the CE, one or more is reallocated as free blocks and used to replace the bad or defective block. When only one or no further unallocated blocks for the CE are available, the FTL places the CE in a read-only mode.

Abstract: At least one data of a set of data stored at a memory cell of a memory component is determined to be associated with an unsuccessful error correction operation. A determination is made as to whether a programming operation associated with the set of data stored at the memory cell has completed. The at least one data of the set of data stored at the memory cell that is associated with the unsuccessful error correction operation is recovered in response to determining that the programming operation has completed. Another memory cell of the memory component is identified in response to recovering the at least one data of the set of data stored at the memory cell that is associated with the unsuccessful error correction operation. The set of data including the recovered at least one data is provided to the other memory cell of the memory component.

Abstract: A memory system includes: a memory device including first memory blocks, within which a single bit is to be programmed into a memory cell by using a single level cell (SLC) method, and second memory blocks, within which two or more bits are to be programmed into a memory cell by using a multi-level cell (MLC)-or-more method, and a controller configured to program first data in the first memory blocks by using the SLC method and then migrate the first data from the first memory blocks into the second memory blocks by using the MLC-or-more method, wherein the controller is further configured to read the first or second memory blocks according to a number of free blocks included in the first memory blocks, when the read request for the second memory block is received after the specific amount of time.

Abstract: Various embodiments set forth techniques for cache warmup. The techniques determining, by a node, identities of one or more target storage blocks of a plurality of storage blocks managed by a storage system, where the node previously cached metadata corresponding to the one or more target storage blocks; receiving the metadata corresponding to the one or more target storage blocks; and storing the metadata corresponding to the one or more target storage blocks in a cache memory of the node.

Abstract: A data transfer device includes: a plurality of masters each having a buffer and configured to calculate a remaining-time counter based on an amount of data in the buffer; a memory system configured to perform data transfer with the plurality of masters and having a memory access prohibition period during which access from the plurality of masters is intermittently prohibited; a bus arbiter configured to arbitrate the plurality of masters based on the remaining-time counter; and a remaining-time counter-adjusting part configured to add a remaining-time counter offset, which adjusts the remaining-time counter until the start of the memory access prohibition period, to at least one of the plurality of masters.

Abstract: The present disclosure generally relates to using irregular MetaBlocks (IRMBs) in both host and control pools. The IRMBs are used to ensure efficient wear leveling. Blocks in the control pool are swapped with blocks in the host pool upon exceeding a program-erase count (PEC) threshold. Additionally, the swapping algorithm for IRMBs can be used to ensure an efficient recovery from an ungraceful shutdown (UGSD) event.

Abstract: A storage device is disclosed. The storage device may comprise storage for input encoded data. A controller may process read requests and write requests from a host computer on the data in the storage. An in-storage compute controller may receive a predicate from the host computer to be applied to the input encoded data. A transcoder may include an index mapper to map an input dictionary to an output dictionary, with one entry in the input dictionary mapped to an entry in the output dictionary, and another entry in the input dictionary mapped to a “don't care” entry in the output dictionary.

Abstract: Embodiments of the present disclosure relate to a memory system and a method for operating the memory system. According to embodiments of the present disclosure, a memory system may determine a target write data which is to be written to one of a plurality of super memory blocks, and may write the target write data based on a size of the target write data, to a first super memory block which includes at least one bad word line or a second super memory block which includes no bad word line.

Abstract: An unbalanced plane management method, an associated data storage device and the controller thereof are provided. The unbalanced plane management method may include: setting an unbalanced plane number; selecting at least one plane with a plane count calculated by subtracting the unbalanced plane number from a maximum plane number, and recording at least one set of blocks of the at least one plane to a block skip table; according to block numbers as indexes, combining blocks of unselected planes into superblocks, wherein said superblocks respectively correspond to said block numbers; and recording total capacity of all superblocks and the unbalanced plane number, to generate a latest record of records of multiple types of storage capacity, for further setting storage capacity configuration of the data storage device, wherein said all superblocks include said superblocks.

Abstract: A data storage device and a selecting bad data block method thereof which includes: writing data to a sample block; reading written data of the sample block as read data; comparing the read data and the written data of each data column in sample block, and calculating a number of error bits in each chunk accordingly; selecting a column with the largest number of error bits in a chunk with the largest number of error bits as a bad data column; and recording the sample block as a bad data block when determining that the number of error bits in the chunk is greater than or equal to the first threshold value and the number of bad columns in the chunk is greater than or equal to the second threshold value.

Abstract: Methods and apparatuses to control digital data transfer via a memory channel between a memory module and a processor are disclosed. At least one of the memory module or the processor coalesces a plurality of short data words into multicast coalesced block data comprising a single data block for transfer via the memory channel. Each of the plurality of short data words pertains to one of at least two partitioned memory submodules in the memory module. The multicast coalesced block data is communicated over the memory channel.

Abstract: System and method for storage data in SSD may be provided. The method may include receiving data writing feature information sent by a file system during an initialization process. The method may include determining, based on the data writing feature information, a size of metadata storage space corresponding to the metadata. The method may further include determining, based on the size of metadata storage space, a target storage region for storing the metadata in the SSD.

Abstract: A method for deleting one or more snapshots using micro-batch processing is provided. The method includes receiving a request to delete the one or more snapshots, identifying one or more middle map extents exclusively owned by the one or more snapshots requested to be deleted, wherein metadata for the one or more snapshots is stored in one or more logical maps having logical map extents mapping logical block addresses (LBAs) to middle block addresses (MBAs) and a middle map having middle map extents mapping MBAs to physical block addresses (PBAs) of physical locations where data blocks are written, adding MBAs of the identified one or more middle map extents in a batch, determining a first micro-batch including a first subset of the MBAs in the batch, the first subset of MBAs being MBAs less than a first upper bound MBA, and using a first transaction to delete the middle map extents corresponding to the first subset of MBAs included in the first micro-batch.

Abstract: A system includes a memory device, and a processing device, operatively coupled with the memory device, to perform operations including receiving a media access operation access command to perform a media access operation with respect to a memory location residing on the memory device, determining whether there exists another memory location access at the memory location, in response to determining that another memory location access exists at the memory location, determining whether the media access operation command is a read command, and in response to determining that the media access operation is a read command, servicing the media access operation command from a media buffer. The media buffer maintains data associated with the completed write operation.

Abstract: An amount of writing data to storage devices can be kept low in additional processing for solving the write hole problem. A storage system includes a computer(s), a nonvolatile storage device(s), and a high-speed storage device(s) which can be accessed at a higher speed than the above-mentioned storage device(s), and a drive log including write log information is recorded in the high-speed storage device. When the computer receives a write request for write data, the computer firstly performs drive log check processing and then performs data write processing.

Abstract: There are provided a memory controller and a storage device including the same. The memory controller includes: a command storage including a first read command queue and a second read command queue; a command generation controller configured to provide an erase command, a suspend command, a resume command, and output a scheduling event signal after the resume command is output; and a command schedule controller configured to: search for a first physical address group, reorder a output sequence of the first read command queue, and provide a command to perform the read command based on the second read command queue.

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to identify a first block family comprising a first set of blocks, wherein the first block family comprises a plurality of blocks that have been programmed within at least one of a specified time window or a specified temperature window; identify a second block family comprising a second set of blocks; and responsive to a determining that a threshold criterion is satisfied, combine the first block family and the second block family by appending, to first block family metadata of the first block family, a record referencing the second set of blocks.

Abstract: A managing method for a flash storage includes: sorting a plurality of blocks within the flash storage into precise blocks and imprecise blocks; and managing the sorted blocks as a plurality of free block pools. The management includes performing garbage collection and wear leveling, and the wear leveling is performed based on CEW (Cumulative Effective Wearing), the CEW indicating cumulative cell damage induced by performing a plurality of operations on a specific block. A storage system includes a memory array; and a memory controller sorting a plurality of blocks of the memory array based on error rates, applying erase voltages corresponding to the error rates, respectively, when data stored in the blocks are erased, controlling each of the erase voltages to have a value scaled down from a standard voltage, and performing incremental step pulse programming on one or more of the blocks.