Abstract: The present disclosure relates to an electronic device. According to the present disclosure, a storage device includes a memory controller acquiring a valid address reflecting a bad block more quickly and a plurality of memory devices each including a plurality of memory blocks included in each of a plurality of planes.

Abstract: A system includes a plurality of integrated circuit (IC) dice having memory cells. A processing device is coupled to the plurality of IC dice, the processing device to perform operations includes: assigning a first stream identifier (ID) to a data type generated by execution of an application within an operating system; associating first files generated by the application with the first stream ID, where the first files are associated with the data type; allocating a first group of memory cells of the plurality of IC dice to the first files, wherein the first group of memory cells is assigned the first stream ID; and causing, based on the first stream ID, the first files to be written sequentially to the first group of memory cells of the plurality of IC dice.

Abstract: The present invention provides a control method of a flash memory controller, wherein the flash memory controller is configured to access a flash memory module, and the control method includes the steps of: receiving a settling command from a host device to configure a portion space of the flash memory module as a zoned namespace; receiving a write command from the host device to write data corresponding a first zone into a plurality of blocks of the flash memory module, wherein an access mode chose by the flash memory controller is determined based on a size of each zone and a size of each block.

Abstract: A plurality of zone reset counters and a global reset counter are maintained. A zone reset counter represents a number of times a respective zone of a memory device has been reset. The global reset counter represents a measure of central tendency of the plurality of zone reset counters. A write command directed to a target zone of the memory device is received, and responsive to determining that a target portion of the target zone is not open, a value of the zone reset counter of het target zone is compared to the value of the global reset counter. If the value of the target zone reset counter equals or exceeds the value of the global reset counter, a portion from a free block list is allocated to the target zone. The allocated portion has a highest program erase count among the one or more portions in free block list.

Abstract: A memory controller includes: a block manager for allocating a plurality of partial super blocks each including partial blocks in different memory blocks; and an operation controller for controlling a plurality of memory devices to perform, in parallel, a program operation of sequentially storing data in physical pages in each of the partial blocks in a partial super block selected from the plurality of partial super blocks. Each of the plurality of partial super blocks includes partial blocks in memory blocks having different numbers of physical pages having an erase state.

Abstract: A processing device of a memory sub-system is configured to sort a plurality of blocks of the memory device; divide the sorted plurality of blocks into a plurality of block segments; scan a first block at a first boundary of a first block segment of the plurality of block segments; scan a second block at a second boundary of the first block segment; identify, based on a scanning result of the first block, a first voltage bin associated with the first block; identify, based on a second scanning result of the second block, a second voltage bin associated with the second block; and responsive to determining that the first voltage bin matches the second voltage bin, assign the first voltage bin to each block of a subset of the plurality of blocks assigned to the first block segment.

Abstract: An electronic system includes a file system configured to assign logical block addresses corresponding to consecutive pieces of data sets of segments in a plurality of zones. The electronic system also includes a memory device including a plurality of memory blocks, and a memory controller configured to map the logical block addresses to physical block addresses corresponding to consecutive pages in the plurality of memory blocks to program the consecutive pieces of data to the consecutive pages in the plurality of memory blocks. The file system is configured to assign new logical block addresses corresponding to consecutive pieces of a data file to invalid segments in the plurality of zones.

Abstract: A nonvolatile memory device may include a plurality of memory regions and a control logic configured to correct a write command transmitted from an external device. The control logic may correct a write command upon determining the suitability of the write command, and perform a write operation on a target memory region based on a corrected write command. The control logic may determine the suitability of the write command based on check information associated with target memory region.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to store XOR parity data in a host memory buffer (HMB) of a host device, monitor a health of the memory device, determine that a threshold corresponding to the health of one or more blocks of the memory device has been reached or exceeded, and copy the XOR parity data from the HMB to the memory device. The controller is further configured to receive a low power mode indication from the host device and enter the low power mode after copying the XOR parity data from the HMB to the memory device. The controller is further configured to correct read failures using the XOR parity data retrieved from the HMB.

Abstract: A data storage system includes a first storage layer, a second storage layer, an I/O manager, and a data organizer. The first storage layer utilizes a first type of data storage device. The first storage layer includes (i) a first data bucket that includes first data having a first data attribute, the first data bucket including a first data limit, and (ii) a second data bucket. The second storage layer utilizes a second type of data storage device. The I/O manager receives a data write request from the user and directs the data write request to the first storage layer. The data organizer (a) determines whether data in the data write request has the first data attribute; and (b) stores the data in the data write request in at least one of the first data bucket and the second data bucket if the data in the data write request has the first data attribute.

Abstract: According to one embodiment, a controller receives from a host a first command for writing data sequentially to a first zone. When buffers include a first buffer to which the first zone is allocated, the controller stores the first data in the first buffer. When the buffers do not include the first buffer but include a free buffer, the controller allocates the first zone to a second buffer that is the free buffer and stores the first data in the second buffer. When the buffers include neither the first buffer nor a free buffer, the controller additionally allocates the first zone to a third buffer of which last update for storing data is the oldest among the buffers, and stores the first data in the third buffer to which the first zone is additionally allocated.

Abstract: A system and associated method for generating a test precondition. The system includes a test device and a storage device including user data blocks and system blocks. The test device reads, from the system blocks, an initial system data snapshot stored and represents a factory format; erases the system blocks and the user data blocks; writes data to selected user data blocks; generates system tables associated with the erasing and writing of the selected user data blocks; replaces the initial system data snapshot with the system tables; writes the replaced system tables to the system blocks; and performs one or more tests on the storage device.

Abstract: There are provided a memory controller and a storage device including the same. The memory controller includes: a command storage including a first read command queue and a second read command queue; a command generation controller configured to provide an erase command, a suspend command, a resume command, and output a scheduling event signal after the resume command is output; and a command schedule controller configured to: search for a first physical address group, reorder a output sequence of the first read command queue, and provide a command to perform the read command based on the second read command queue.

Abstract: Techniques for managing storage blocks involve: according to a first request for allocating a target number of consecutive storage blocks from a storage device, querying an index table that is used to record index information of a plurality of groups of consecutive idle storage blocks in the storage device to determine a first group of consecutive idle storage blocks from the plurality of groups of consecutive idle storage blocks; allocating the target number of consecutive storage blocks from the first group of consecutive idle storage blocks; updating a bitmap that is used to record states of a plurality of storage blocks in the storage device; and updating first index information of the first group of consecutive idle storage blocks recorded in the index table. Accordingly, such techniques may reduce storage complexity and improve system performance.

Abstract: A method includes determining that a ratio of valid data portions of a block of memory cells is greater than or less than a valid data portion threshold and performing a first media management operation on the block of memory cells in response to determining that the ratio of valid data portions is greater than the valid data portion threshold. The method further includes performing a second media management operation on the block of memory cells in response to determining that the ratio of valid data portions is less than the valid data portion threshold.

Abstract: A storage system has a pool of reserved memory blocks that can be used either as control blocks or as overprovision blocks. A controller in the storage system can dynamically allocate one or more blocks reserved for control blocks as extra overprovision blocks. If the storage system is running low on control blocks, the controller can allocate the extra blocks from overprovision pool back as control blocks.

Abstract: Systems and methods for dynamic and adaptive interrupt coalescing are disclosed. NVM Express (NVMe) implements a paired submission queue and completion queue mechanism, with host software on the host device placing commands into the submission queue. The memory device notifies the host device, via an interrupt, of entries on the completion queue. Responsive to receiving the interrupt, the host device access the completion queue to access entries placed by the memory device therein. The host device may take a certain amount of time to service the interrupt resulting in host latency. Given knowledge of the host latency, the memory device time the sending of the interrupt so that, given the host latency, the memory device may post the entry to the completion queue in a timely manner.

Abstract: A multi-rank memory system in which calibration operations are performed between a memory controller and one rank of memory while data is transferred between the controller and other ranks of memory. A memory controller performs a calibration operation that calibrates parameters pertaining to transmission of data via a first data bus between the memory controller and a memory device in a first rank of memory. While the controller performs the calibration operation, the controller also transfers data with a memory device in a second rank of memory via a second data bus.

Abstract: A key-value storage device includes a non-volatile memory (NVM) divided into blocks, and a data buffer including a key buffer, a value buffer and a mapping buffer, and a controller including a key-value manager. The key-value manager receives a command and key-pairs including keys and values respectively corresponding to the keys, separates the keys from the values, store the keys in the key buffer and store the values in the value buffer, generates a value stream by combining a set of values stored in the key buffer, generates a key stream by combining a set of keys and merging indices for values respectively corresponding to the keys in the set of keys, and updates a key matrix stored in the mapping buffer and indicating whether an index among the indices of the key stream is related to each one of the blocks of the NVM.

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to create a first block family comprising a first set of blocks that have been programmed within at least one of a first specified time window or a first specified temperature window, wherein each block associated with the first block family is associated with a first set of read level offsets; create, a second block family comprising a second set of blocks that have been programmed within at least one of a second specified time window following the first specified time window or a second specified temperature window, wherein each block associated with the second block family is associated with a second set of read level offsets; and responsive to a determining that a threshold criterion is satisfied, combine the first and second block family.