Patents Examined by Francisco A Grullon
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Patent number: 11755252Abstract: A plurality of computing devices are communicatively coupled to each other via a network, and each of the plurality of computing devices is operably coupled to one or more of a plurality of storage devices. A plurality of failure resilient stripes is distributed across the plurality of storage devices such that each of the plurality of failure resilient stripes spans a plurality of the storage devices. The plurality of computing devices maintains each failure resilient stripe using a bucket. These buckets are operably split and transferred between the computing devices to balance available computing power and storage access.Type: GrantFiled: October 8, 2021Date of Patent: September 12, 2023Inventors: Maor Ben Dayan, Omri Palmon, Liran Zvibel, Kanael Arditti
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Patent number: 11748030Abstract: An illustrative method includes receiving, by an integrated storage manager from an operating system level virtualization service, a request to perform an operation with respect to one or more storage systems; determining, by the integrated storage manager, multiple versions of a performance impact among the one or more storage systems based on potentially implementing the request in multiple ways; and implementing, by the integrated storage manager based on the determining of the multiple versions of the performance impact, the request in a particular way that improves one or more storage system metrics of the one or more storage systems.Type: GrantFiled: November 17, 2020Date of Patent: September 5, 2023Assignee: Pure Storage, Inc.Inventor: Patrick East
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Patent number: 11733931Abstract: A central processing unit of a host system is used to manage at least a portion of a data placement of a storage device including by bypassing a storage controller processing unit of the storage device to store data in a random-access memory of the storage device while allowing media endurance management of the storage device to be managed by the storage controller processing unit of the storage device. The central processing unit of the host system to the storage device provides a command that causes the storage controller processing unit of the storage device to utilize the data stored by the central processing unit of the host system in the random-access memory of the storage device.Type: GrantFiled: July 13, 2020Date of Patent: August 22, 2023Assignee: Meta Platforms, Inc.Inventors: Ta-Yu Wu, Akshat Nanda
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Patent number: 11709607Abstract: Aspects include obtaining data to be transformed. A selected transformation to be applied to the data is determined based on a storage block address list entry (SBALE) in a storage block address list (SBAL). The SBALE includes at least one field that is used in determining the selected transformation to be applied. The selected transformation is applied on the data to generate transformed data and the transformed data is placed in a location specified by the SBAL.Type: GrantFiled: September 15, 2021Date of Patent: July 25, 2023Assignee: International Business Machines CorporationInventors: Luke Hopkins, Michael James Becht, Christopher J. Colonna, Stephen Robert Guendert, Pasquale A. Catalano
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Patent number: 11698729Abstract: Various implementations described herein relate to systems and methods for predicting and managing drive hazards for Solid State Drive (SSD) devices in a data center, including receiving telemetry data corresponding to SSDs, determining future hazard of one of those SSDs based on an a-priori model or machine learning, and causing migration of data from that SSD to another SSD.Type: GrantFiled: May 23, 2022Date of Patent: July 11, 2023Assignee: KIOXIA CORPORATIONInventors: Yaron Klein, Verly Gafni-Hoek
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Patent number: 11698750Abstract: Technology is disclosed herein for efficient use of volatile memory that is used for accumulating parity data of user data being written to non-volatile memory cells. A memory controller may replace primary parity in a first portion of a parity buffer with data other than primary parity while a second portion of the buffer is still being used to store the primary parity. Therefore, the memory controller smartly re-uses the parity buffer, which makes efficient use of the volatile memory. In one aspect, a memory controller accumulates secondary parity for the user data in a first portion of the parity buffer while a second portion of the parity buffer is still being used to store the primary parity. The memory controller may compute the secondary parity from present content of the first portion of the parity buffer and primary parity presently stored in the second portion of the buffer.Type: GrantFiled: October 4, 2021Date of Patent: July 11, 2023Assignee: SanDisk Technologies LLCInventors: Bhanushankar Doni, Pratik Bhatt
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Patent number: 11698738Abstract: A multi-namespace storage device includes a nonvolatile memory which includes a first memory block and a second memory block different from the first memory block, and a memory controller which receives, from a host, a command for requesting creation of a first namespace including a first logical block number and a second namespace including a second logical page number not included in the first logical block number and receives a physical mapping command for instructing physical mapping of the first namespace. The memory controller performs a first mapping operation by mapping the first logical block number to the first memory block and performs a second mapping operation by mapping the second logical page number to a second memory page included in the second memory block in response to the physical mapping command.Type: GrantFiled: July 22, 2021Date of Patent: July 11, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Hyun-Jin Kim
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Patent number: 11698739Abstract: A memory system includes a plurality of memory devices and a controller, wherein each of the plurality of memory devices includes zone blocks. The controller is configured to evenly distribute open zone blocks within the memory devices by referring to an activated zone block count table and a full zone block count table. The activated zone block count table includes an activated zone block count of each of the memory devices, and the full zone block count table includes a full zone block count of each of the memory devices.Type: GrantFiled: October 20, 2021Date of Patent: July 11, 2023Assignee: SK hynix Inc.Inventor: Soon Yeal Yang
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Patent number: 11693570Abstract: A system and method improve caching efficiency in a data storage system by performing machine learning processes on metadata relating to extents of data blocks, rather than individual blocks themselves. Thus, once the storage devices are divided into extents, various metadata regarding access to the blocks within each extent are aggregated, and per-extent features are extracted. These features are used to train a data regression model that is subsequently used to infer a most likely “hotness” value for each extent at a future time. These predicted values, which may be further classified as e.g. “hot”, “warm”, and “cold” using thresholds, are used to implement the cache replacement policy. Embodiments scale to large and multi-layered caches, and may avoid common caching problems like thrashing, by adjusting the extent size. Policy goal functions may be optimized by dynamically adjusting the classification thresholds.Type: GrantFiled: April 29, 2021Date of Patent: July 4, 2023Assignee: EMC IP Holding Company LLCInventors: Vamsi Vankamamidi, Shaul Dar
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Patent number: 11687262Abstract: Memory systems and methods of operating the memory systems are disclosed. A memory system including a plurality of data storage zones may comprise a memory device including a plurality of zones for storing data, and a memory controller configured to control the memory device in performing a write operation in the memory device. The memory controller is configured to, upon performing a write operation corresponding to a write request received from a host, update a logical write pointer and a physical write pointer associated with a zone that is targeted to perform the write operation corresponding to the write request received from the host, and upon performing a write operation corresponding an internal write command internally issued by the memory controller, update a physical write pointer associated with the zone that is targeted to perform the write operation corresponding to an internal write command issued by the memory controller.Type: GrantFiled: April 20, 2021Date of Patent: June 27, 2023Assignee: SK hynix Inc.Inventors: In Mo Kwak, Jeong Su Park
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Patent number: 11675510Abstract: Systems and methods for scalable shared memory among networked devices comprising IP addressable memory blocks is disclosed. The disclosed systems and methods comprise a communications network, one or more memory lending devices, each comprising one or more allocated and/or available uniformly sized blocks of memory remotely lendable over the communications network, wherein each of the one or more blocks of memory are uniquely addressable over the communications network using an Internet Protocol (IP) destination address. The systems and methods comprise further comprise at least one memory borrowing device comprising one or more remote blocks of memory allocated (loaned) thereto, wherein the at least one memory borrowing device is configured to individually access each of the one or more remote blocks of memory allocated thereto over the communications network using a unique Internet Protocol (IP) destination address.Type: GrantFiled: May 12, 2022Date of Patent: June 13, 2023Inventor: Xiaoliang Zhao
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Patent number: 11675705Abstract: An indication to perform an eviction operation on a cache line in a cache can be received. A determination can be made as to whether at least one sector of the cache line is associated with invalid data. In response to determining that at least one sector of the cache line is associated with invalid data, a read operation can be performed to retrieve valid data associated with the at least one sector. The at least one sector of the cache line that is associated with the invalid data can be modified based on the valid data. Furthermore, the eviction operation can be performed on the cache line with the modified at least one sector.Type: GrantFiled: March 11, 2021Date of Patent: June 13, 2023Assignee: Micron Technology, Inc.Inventors: Dhawal Bavishi, Robert M. Walker
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Patent number: 11675511Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to perform operations comprising assigning a plurality of data streams to a block family comprising a plurality of blocks of a memory device; responsive to programming a first block associated with a first data stream of the plurality of data streams, associating the first block with the block family; and responsive to programming a second block associated with a second data stream of the plurality of data streams, associating the second block with the block family.Type: GrantFiled: June 22, 2022Date of Patent: June 13, 2023Assignee: Micron Technology, Inc.Inventors: Michael Sheperek, Bruce A. Liikanen, Peter Feeley, Larry J. Koudele, Shane Nowell, Steven Michael Kientz
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Patent number: 11669258Abstract: Methods, systems, and devices for dynamic superblocks are described. In some examples, a superblock may be established across one or more dice of a memory device. A superblock may include one or more blocks from a plurality of planes of a memory die, and may be associated with a first performance cursor or a second performance cursor. The superblock may be established based on one or more criteria, such as a quantity of available blocks in a plane, a quantity of access operations performed on one or more blocks in a plane, or other criteria. Establishing a superblock associated with a first performance cursor may allow for performance criteria established by a host device to be maintained, while establishing a superblock associated with a second performance cursor may allow for garbage collection, wear leveling, and other maintenance operations to be performed on the memory device.Type: GrantFiled: April 27, 2021Date of Patent: June 6, 2023Assignee: Micron Technology, Inc.Inventor: Giuseppe Cariello
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Patent number: 11669277Abstract: A computer system having a host coupled to a storage device via a peripheral component interconnect express bus. The host communicates write commands of low priority to the storage device, which places them in a queue for execution at an idle time. In response to a determination that the storage device is in an idle state, the storage device best accommodates the write commands in the idle queue in connection with housekeeping tasks, such as garbage collection and wear leveling, to best reduce write amplification.Type: GrantFiled: July 23, 2021Date of Patent: June 6, 2023Assignee: Micron Technology, Inc.Inventor: Alex Frolikov
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Patent number: 11662950Abstract: The present disclosure is related to performing speculation in, for example, a memory device or a computing system that includes a memory device. Speculation can be used to identify data that is accessed together or to predict data that will be accessed with greater frequency. The identified data can be organized to improve efficiency in providing access to the data.Type: GrantFiled: October 14, 2021Date of Patent: May 30, 2023Assignee: Micron Technology, Inc.Inventors: Richard C. Murphy, Glen E. Hush, Honglin Sun
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Patent number: 11656778Abstract: A computer storage device having a host interface, a controller, non-volatile storage media, and firmware. The firmware instructs the controller to select a block size for allocating blocks to namespaces based on a storage capacity of the non-volatile storage media. Various requests by a host to create namespaces are received by the controller via the host interface. After each request is received, the controller allocates blocks to the requested namespace using the selected block size. The controller can select the block size at the time of initial manufacture or operation, and/or can dynamically select various block sizes during operation of the storage device. Dynamic selection of the block size can be based on signaling from sensors of the storage device and/or host.Type: GrantFiled: August 17, 2021Date of Patent: May 23, 2023Assignee: Micron Technology, Inc.Inventor: Alex Frolikov
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Patent number: 11650747Abstract: Disclosed are various embodiments for high throughput reclamation of pages in memory. A first plurality of pages in a memory of the computing device are identified to reclaim. In addition, a second plurality of pages in the memory of the computing device are identified to reclaim. The first plurality of pages are prepared for storage on a swap device of the computing device. Then, a write request is submitted to a swap device to store the first plurality of pages. After submission of the write request, the second plurality of pages are prepared for storage on the swap device while the swap device completes the write request.Type: GrantFiled: June 10, 2021Date of Patent: May 16, 2023Assignee: VMware, Inc.Inventors: Emmanuel Amaro Ramirez, Marcos Kawazoe Aguilera, Pratap Subrahmanyam, Rajesh Venkatasubramanian
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Patent number: 11630592Abstract: A method and apparatus for a database management architecture on an SSD. A list of tables is stored in the SSD, and records of a table are stored across multiple FIMs of the SSD such that a group of records may be read in parallel by concurrently reading from multiple FIMs. The records of the table are stored on jumboblocks, organized in an unordered fashion as a linked list. New records are added to the end of the linked list. Records having gaps resulting from data modification or bad portions of an NVM die are re-organized via garbage collection when the gap memory size reaches about 20% of table memory size.Type: GrantFiled: February 22, 2021Date of Patent: April 18, 2023Assignee: Western Digital Technologies, Inc.Inventors: Israel Zimmerman, Eyal Hakoun, Judah Gamliel Hahn
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Patent number: 11620049Abstract: Techniques involve: determining, based on sizes of a storage space used by a file system at a set of historical moments and a current moment, predicted sizes of a storage space to be used by the file system at a plurality of future moments. The techniques further involve: determining sizes of an available storage space and available durations of a set of candidate future moments in the plurality of future moments based on the predicted sizes. The techniques further involve: determining, based on the sizes of the available storage space and the available durations of the set of candidate future moments, predicted values that characterize available storage capacities of the set of candidate future moments. The techniques further involve: determining a target moment from the set of candidate future moments based on the predicted values to recycle at least part of an available storage space of the target moment.Type: GrantFiled: September 24, 2020Date of Patent: April 4, 2023Assignee: EMC IP Holding Company LLCInventors: Changxu Jiang, Fei Wang